Glossary of various terms

CLB: Configurable Logic Block - Xilinx term. Contains a group of slices and is the structure that repeats throughout the device. Similar to Altera LAB or iCE40 "logic tile" except a CLB usually contains multiple slices.

LAB: Logic Array Block - Altera term. Refers to a grouping of LEs (containing LUTs and flip-flops) with a common local interconnect. Analogous to Xilinx "slice" or iCE40 "logic tile."

LC: Logic Cell - Lattice term. Refers to a grouping of a LUT, a flip-flop, and miscellaneous other bits (e.g. carry chains). Analogous to Altera "LE."

LE: Logic Element - Altera term. Refers to a grouping of a LUT, a flip-flop, and miscellaneous other bits (e.g. carry chains). Analogous to iCE40 "LC."

LUT: Look-up table - used to implement arbitrary combinatorial logic functions. LUTn with n a number usually means this table has n inputs.

ROM/PROM/EPROM-as-logic: In here for completeness. Behaves like a programmable logic device that implements logic using a sum-of-products structure have a programmable OR array and a fixed AND array.

PAL: Programmable Array Logic - classic type of programmable logic device that implements logic using a sum-of-products structure (AND gates chaining into OR gates). PAL devices have a fixed OR array (which AND gates connect to which OR gates is not programmable) and a programmable AND array. This term is also used in CPLDs to refer to similarly-designed structures.

PLA: Programmable Logic Array - programmable logic device that implements logic using a sum-of-products structure (AND gates chaining into OR gates). PLA devices have a programmable OR array and a programmable AND array. This term is also used in CPLDs to refer to similarly-designed structures.