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* Added RISCV dir to contain the RISCV architecture engine code. Adding the TableGen files generated from llvm-tblgen. Add Disassembler.h * Started working on RISCVDisassembler.c - RISCV_init(), RISCVDisassembler_getInstruction, and RISCV_getInstruction * Added all functions to RISCVDisassembler.c and needed modifications to RISCVGenDisassemblerTables.inc. Add and modified RISCVGenSubtargetInfo.inc. Start creation of RISCVInstPrinter.h * Finished RISCVGenAsmWriter.inc. Finished RISCVGenRegisterInfo.inc. Minor fixes to RISCVDisassembler.c. Working on RISCVInstPrinter * Finished RISCVInstPrinter, RISCVMapping, RISCVBaseInfo, RISCVGenInstrInfo.inc, RISCVModule.c. Working on riscv.h * Backport it from: porto703@0db412c * All RISCV files added. Compiled correctly and initial test for ADD, ADDI, AND works properly. * Add refactored cs.c for RISCV * Testing all I instructions in test_riscv.c * Modify the orignal backport for RISCVGenRegisterInfo.inc, capstone.h and test_iter to work w/ the current code strcuture * Fix issue with RISCVGenRegisterInfo.inc - RISCVRegDesc[] (Excess elements in struct initializer). Added RISCV tests to test_iter.c * fixed bug related to incorrect initialization of memory after malloc * fix compile bug * Fix compile errors. * move riscv.h to include/capstone * fix indentation issues * fix coding style issues * Fix indentation issues * fix coding style * Move variable declaration to the top of the block * Fix coding indentation * Move some stuff into RISCVMappingInsn.inc * Fix code sytle * remove cs_mode support for RISCV * update asmwriter-inc to LLVM upstream * update the .inc files to riscv upstream * update riscv disassembler function for suport 16bit instructions * update printer & tablegen inc files which have fixed arguments mismatch * update headers and mapping source * add riscv architecture specific test code * fix all RISCV tons of compiler errors * pass final tests * add riscv tablegen patchs * merge with upstream/next * fix cstool missing riscv file * fix root Makefile * add new TableGen patchs for riscv * fix cmakefile.txt of missing one riscv file * fix declaration conflict * fix incompatible declaration type * change riscvc from arch to mode * fix test_riscv warnning * fix code style and add riscv part of test_basic * add RISCV64 mode * add suite for riscv * crack fuzz test * fix getfeaturebits test add riscvc * fix test missing const qualifier warnning * fix testcase type mismatch * fix return value missing * change getfeaturebits test * add test cs files * using a winder type contain the decode string * fix a copy typo * remove useless mode for riscv * change cs file blank type * add repo for update_riscv & fix cstool missing riscv mode * fix typo * add riscv for cstool useage * add TableGen patch for riscv asmwriter * clean ctags file * remove black comment line * fix fuzz related something * fix missing RISCV string of fuzz * update readme, etc.. * add riscv *.s.cs file * add riscv *.s.cs file & clear ctags * clear useless array declarations at capstone_test * update to 5e4069f * update readme change name more formal * change position of riscv after bpf and modify copyright more uniform * clear useless ctags file * change blank with tab in riscv.h * add riscv python bindings * add riscv in __init__.py * fix riscv define value for python binding * fix test_riscv.py typo * add missing riscvc in __init__.py of python bindings * fix alias-insn printer bug, remove useless newline * change inst print delimter from tab to bankspace for travis * add riscv tablegen patch * fix inst output more consistency * add TableGen patch which fix inst output formal * crack the effective address output for detail and change register print function * fix not detail crash bug * change item declaration position at cs_riscv * update riscv.py * change function name more meaningfull * update python binding makefile * fix register enum sequence according to riscvgenreginfo.inc * test function name * add enum s0/fp in riscv.h & update riscv_const.py * add register name enum
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,106 @@ | ||
| //===-- RISCVBaseInfo.h - Top level definitions for RISCV MC ----*- C++ -*-===// | ||
| // | ||
| // The LLVM Compiler Infrastructure | ||
| // | ||
| // This file is distributed under the University of Illinois Open Source | ||
| // License. See LICENSE.TXT for details. | ||
| // | ||
| //===----------------------------------------------------------------------===// | ||
| // | ||
| // This file contains small standalone enum definitions for the RISCV target | ||
| // useful for the compiler back-end and the MC libraries. | ||
| // | ||
| //===----------------------------------------------------------------------===// | ||
| #ifndef CS_RISCVBASEINFO_H | ||
| #define CS_RISCVBASEINFO_H | ||
| #include <assert.h> | ||
|
|
||
| //#include "RISCVMCTargetDesc.h" | ||
|
|
||
| // RISCVII - This namespace holds all of the target specific flags that | ||
| // instruction info tracks. All definitions must match RISCVInstrFormats.td. | ||
| enum { | ||
| IRISCVII_InstFormatPseudo = 0, | ||
| IRISCVII_InstFormatR = 1, | ||
| IRISCVII_InstFormatR4 = 2, | ||
| IRISCVII_InstFormatI = 3, | ||
| IRISCVII_InstFormatS = 4, | ||
| IRISCVII_InstFormatB = 5, | ||
| IRISCVII_InstFormatU = 6, | ||
| IRISCVII_InstFormatJ = 7, | ||
| IRISCVII_InstFormatCR = 8, | ||
| IRISCVII_InstFormatCI = 9, | ||
| IRISCVII_InstFormatCSS = 10, | ||
| IRISCVII_InstFormatCIW = 11, | ||
| IRISCVII_InstFormatCL = 12, | ||
| IRISCVII_InstFormatCS = 13, | ||
| IRISCVII_InstFormatCA = 14, | ||
| IRISCVII_InstFormatCB = 15, | ||
| IRISCVII_InstFormatCJ = 16, | ||
| IRISCVII_InstFormatOther = 17, | ||
|
|
||
| IRISCVII_InstFormatMask = 31 | ||
| }; | ||
|
|
||
| enum { | ||
| RISCVII_MO_None, | ||
| RISCVII_MO_LO, | ||
| RISCVII_MO_HI, | ||
| RISCVII_MO_PCREL_HI, | ||
| }; | ||
|
|
||
| // Describes the predecessor/successor bits used in the FENCE instruction. | ||
| enum FenceField { | ||
| RISCVFenceField_I = 8, | ||
| RISCVFenceField_O = 4, | ||
| RISCVFenceField_R = 2, | ||
| RISCVFenceField_W = 1 | ||
| }; | ||
|
|
||
| // Describes the supported floating point rounding mode encodings. | ||
| enum RoundingMode { | ||
| RISCVFPRndMode_RNE = 0, | ||
| RISCVFPRndMode_RTZ = 1, | ||
| RISCVFPRndMode_RDN = 2, | ||
| RISCVFPRndMode_RUP = 3, | ||
| RISCVFPRndMode_RMM = 4, | ||
| RISCVFPRndMode_DYN = 7, | ||
| RISCVFPRndMode_Invalid | ||
| }; | ||
|
|
||
| inline static const char *roundingModeToString(enum RoundingMode RndMode) | ||
| { | ||
| switch (RndMode) { | ||
| default: | ||
| assert(0 && "Unknown floating point rounding mode"); | ||
| case RISCVFPRndMode_RNE: | ||
| return "rne"; | ||
| case RISCVFPRndMode_RTZ: | ||
| return "rtz"; | ||
| case RISCVFPRndMode_RDN: | ||
| return "rdn"; | ||
| case RISCVFPRndMode_RUP: | ||
| return "rup"; | ||
| case RISCVFPRndMode_RMM: | ||
| return "rmm"; | ||
| case RISCVFPRndMode_DYN: | ||
| return "dyn"; | ||
| } | ||
| } | ||
|
|
||
| inline static bool RISCVFPRndMode_isValidRoundingMode(unsigned Mode) | ||
| { | ||
| switch (Mode) { | ||
| default: | ||
| return false; | ||
| case RISCVFPRndMode_RNE: | ||
| case RISCVFPRndMode_RTZ: | ||
| case RISCVFPRndMode_RDN: | ||
| case RISCVFPRndMode_RUP: | ||
| case RISCVFPRndMode_RMM: | ||
| case RISCVFPRndMode_DYN: | ||
| return true; | ||
| } | ||
| } | ||
|
|
||
| #endif |
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