Name		Name	Last commit message	Last commit date
Latest commit History 44 Commits
ALU		ALU
DoorLockSystem		DoorLockSystem
FPGAAdvancedDesign		FPGAAdvancedDesign
FPGADigitalClock		FPGADigitalClock
FPGALightController		FPGALightController
SequentialLogicDesign		SequentialLogicDesign
README.md		README.md
vhdl.md		vhdl.md

Repository files navigation

VHDL-Projects

Design and verification of various digital systems. Synthesized RTL code and programmed to DE1-SoC FPGA.

2 stars

1 watching