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[Deepin-Kernel-SIG] [linux 6.12-y] [Upstream] Merge x86,tlb: context switch optimizations #1214
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[Deepin-Kernel-SIG] [linux 6.12-y] [Upstream] Merge x86,tlb: context switch optimizations #1214
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mainline inclusion from mainline-v6.14-rc1 category: performance On busy multi-threaded workloads, there can be significant contention on the mm_cpumask at context switch time. Reduce that contention by updating mm_cpumask lazily, setting the CPU bit at context switch time (if not already set), and clearing the CPU bit at the first TLB flush sent to a CPU where the process isn't running. When a flurry of TLB flushes for a process happen, only the first one will be sent to CPUs where the process isn't running. The others will be sent to CPUs where the process is currently running. On an AMD Milan system with 36 cores, there is a noticeable difference: $ hackbench --groups 20 --loops 10000 Before: ~4.5s +/- 0.1s After: ~4.2s +/- 0.1s Signed-off-by: Rik van Riel <[email protected]> Signed-off-by: Ingo Molnar <[email protected]> Cc: Dave Hansen <[email protected]> Cc: Linus Torvalds <[email protected]> Cc: Peter Zijlstra <[email protected]> Cc: Mel Gorman <[email protected]> Link: https://lore.kernel.org/r/[email protected] (cherry picked from commit 209954c) Signed-off-by: Wentao Guan <[email protected]>
mainline inclusion from mainline-v6.14-rc1 category: performance Add a tracepoint when we send a TLB flush IPI to a CPU that used to be in the mm_cpumask, but isn't any more. Suggested-by: Dave Hansen <[email protected]> Signed-off-by: Rik van Riel <[email protected]> Signed-off-by: Ingo Molnar <[email protected]> Link: https://lore.kernel.org/r/[email protected] (cherry picked from commit 2815a56) Signed-off-by: Wentao Guan <[email protected]>
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[APPROVALNOTIFIER] This PR is NOT APPROVED This pull-request has been approved by: The full list of commands accepted by this bot can be found here.
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mainline inclusion from mainline-v6.16-rc1 category: bugfix The CONFIG_DEBUG_VM=y warning in switch_mm_irqs_off() started triggering in testing: VM_WARN_ON_ONCE(prev != &init_mm && !cpumask_test_cpu(cpu, mm_cpumask(prev))); AFAIU what happens is that unuse_temporary_mm() clears the mm_cpumask() for the current CPU, while switch_mm_irqs_off() then checks that the mm_cpumask() bit is set for the current CPU. While this behaviour hasn't really changed since the following commit: 209954c ("x86/mm/tlb: Update mm_cpumask lazily") introduced both, but the warning is wrong, so remove it. [ mingo: Patchified Peter's email. ] Reported-by: [email protected] Reported-by: Borislav Petkov <[email protected]> Signed-off-by: Peter Zijlstra <[email protected]> Signed-off-by: Ingo Molnar <[email protected]> Cc: Andy Lutomirski <[email protected]> Cc: Brian Gerst <[email protected]> Cc: Juergen Gross <[email protected]> Cc: Andrew Cooper <[email protected]> Cc: Rik van Riel <[email protected]> Cc: "H. Peter Anvin" <[email protected]> Cc: Linus Torvalds <[email protected]> Cc: [email protected] Link: https://lore.kernel.org/r/[email protected] (cherry picked from commit 52ebfe7) Signed-off-by: Wentao Guan <[email protected]> Conflicts: arch/x86/mm/tlb.c
deepin pr auto review这段代码是关于x86架构下内存管理(MM)和TLB(转换后备缓冲器)处理的修改。我来分析一下这些变更并提供审查意见: 1. 代码变更概述
2. 语法逻辑分析
3. 代码质量改进建议
4. 代码性能分析
5. 代码安全性分析
6. 总体建议
这些修改看起来是为了解决TLB刷新相关的问题,特别是处理远程CPU上的TLB刷新。虽然修改的目的是合理的,但实现方式可能需要更多的测试和验证,以确保不会引入新的问题。 |
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Pull Request Overview
This PR merges x86 TLB context switch optimizations that improve TLB (Translation Lookaside Buffer) management during process context switches. The changes optimize when CPUs are added/removed from memory management unit CPU masks and add better tracking for remote TLB flush scenarios.
- Adds new TLB flush reason
TLB_REMOTE_WRONG_CPUfor better debugging/tracing - Optimizes CPU mask management by deferring CPU removal until actually needed
- Improves temporary memory management for code patching operations
Reviewed Changes
Copilot reviewed 3 out of 3 changed files in this pull request and generated no comments.
| File | Description |
|---|---|
| include/linux/mm_types.h | Adds new TLB flush reason enum for wrong CPU scenarios |
| arch/x86/mm/tlb.c | Optimizes context switching by deferring cpumask operations and adding CPU clearing logic |
| arch/x86/kernel/alternative.c | Moves variable declarations and adds cpumask clearing for temporary mm operations |
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x86,tlb: context switch optimizations
https://lore.kernel.org/all/[email protected]/