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Verilog: empty module/generate item
This adds support for empty module items.
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8 files changed

+32
-0
lines changed

8 files changed

+32
-0
lines changed
Lines changed: 7 additions & 0 deletions
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@@ -0,0 +1,7 @@
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CORE
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empty_item.v
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^no properties$
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^EXIT=10$
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^SIGNAL=0$
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--
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module main;
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// The empty item.
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;
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generate
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// Also inside generate
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;
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endgenerate
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endmodule

src/hw_cbmc_irep_ids.h

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@@ -136,6 +136,7 @@ IREP_ID_ONE(offset)
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IREP_ID_ONE(xnor)
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IREP_ID_ONE(specify)
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IREP_ID_ONE(verilog_module)
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IREP_ID_ONE(verilog_empty_item)
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IREP_ID_ONE(module_source)
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IREP_ID_ONE(module_items)
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IREP_ID_ONE(parameter_port_list)

src/verilog/parser.y

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@@ -1062,6 +1062,8 @@ package_or_generate_item_declaration:
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that let constructs may be declared in a
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module/interface/program/checker etc. */
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| let_declaration
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| ';'
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{ init($$, ID_verilog_empty_item); }
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;
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// System Verilog standard 1800-2017

src/verilog/verilog_elaborate.cpp

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@@ -768,6 +768,9 @@ void verilog_typecheckt::collect_symbols(
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{
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collect_symbols(to_verilog_let(module_item));
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}
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else if(module_item.id() == ID_verilog_empty_item)
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{
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}
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else
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DATA_INVARIANT(false, "unexpected module item: " + module_item.id_string());
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}

src/verilog/verilog_interfaces.cpp

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@@ -274,6 +274,9 @@ void verilog_typecheckt::interface_module_item(
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{
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// already done during constant elaboration
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}
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else if(module_item.id() == ID_verilog_empty_item)
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{
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}
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else
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{
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DATA_INVARIANT(false, "unexpected module item: " + module_item.id_string());

src/verilog/verilog_synthesis.cpp

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@@ -2629,6 +2629,9 @@ void verilog_synthesist::synth_module_item(
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{
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// done already
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}
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else if(module_item.id() == ID_verilog_empty_item)
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{
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}
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else
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{
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throw errort().with_location(module_item.source_location())

src/verilog/verilog_typecheck.cpp

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@@ -1629,6 +1629,9 @@ void verilog_typecheckt::convert_module_item(
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{
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// done already
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}
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else if(module_item.id() == ID_verilog_empty_item)
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{
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}
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else
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{
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throw errort().with_location(module_item.source_location())

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