Verilog: make net_decl_assignment rule match SystemVerilog 1800-2017

This removes the net_name rule, and makes the assignment in the
net_decl_assignment rule optional, to match SystemVerilog 1800-2017.

Author: kroening

src/verilog/parser.y

@@ -1160,12 +1160,7 @@ genvar_declaration:
 	;
 
 net_declaration:
-          net_type drive_strength_opt vectored_scalared_opt data_type_or_implicit delay3_opt list_of_net_names ';'
-		{ init($$, ID_decl);
-                  addswap($$, ID_class, $1);
-                  addswap($$, ID_type, $4);
-                  swapop($$, $6); }
-        | net_type drive_strength_opt vectored_scalared_opt data_type_or_implicit delay3_opt list_of_net_decl_assignments ';'
+          net_type drive_strength_opt vectored_scalared_opt data_type_or_implicit delay3_opt list_of_net_decl_assignments ';'
 		{ init($$, ID_decl);
                   addswap($$, ID_class, $1);
                   addswap($$, ID_type, $4);
@@ -1195,21 +1190,6 @@ vectored_scalared_opt:
 	| TOK_SCALARED     { init($$, "scalared"); }
 	;
 
-list_of_net_names:
-	  net_name
-		{ init($$); mto($$, $1); }
-	| list_of_net_names ',' net_name
-		{ $$=$1;    mto($$, $3); }
-	;
-
-net_name: net_identifier unpacked_dimension_brace
-          {
-            $$=$1;
-            stack_expr($$).id(ID_declarator);
-            addswap($$, ID_type, $2);
-          }
-	;
-
 list_of_net_decl_assignments:
 	  net_decl_assignment
 		{ init($$); mto($$, $1); }
@@ -1673,7 +1653,10 @@ range:	part_select;
 // System Verilog standard 1800-2017
 // A.2.4 Declaration assignments
 
-net_decl_assignment: net_identifier '=' expression
+net_decl_assignment:
+	  net_identifier
+		{ $$ = $1; stack_expr($$).id(ID_declarator); }
+	| net_decl_assignment: net_identifier '=' expression
 		{ $$ = $1; stack_expr($$).id(ID_declarator); addswap($$, ID_value, $3); }
 	;