Skip to content

Commit f7cf3fd

Browse files
committed
Verilog: distinguish packed and unpacked arrays
This adds two new IDs to distinguish packed and unpacked arrays in the Verilog parse tree.
1 parent 3fc2299 commit f7cf3fd

File tree

5 files changed

+20
-11
lines changed

5 files changed

+20
-11
lines changed

src/hw_cbmc_irep_ids.h

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -106,9 +106,11 @@ IREP_ID_ONE(wire)
106106
IREP_ID_ONE(uwire)
107107
IREP_ID_ONE(wand)
108108
IREP_ID_ONE(automatic)
109-
IREP_ID_ONE(verilog_enum)
110109
IREP_ID_TWO(C_verilog_type, #verilog_type)
110+
IREP_ID_ONE(verilog_enum)
111+
IREP_ID_ONE(verilog_packed_array)
111112
IREP_ID_ONE(verilog_type_reference)
113+
IREP_ID_ONE(verilog_unpacked_array)
112114
IREP_ID_ONE(enum_names)
113115
IREP_ID_ONE(var)
114116
IREP_ID_ONE(trireg)

src/verilog/parser.y

Lines changed: 5 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1202,7 +1202,7 @@ list_of_net_names:
12021202
{ $$=$1; mto($$, $3); }
12031203
;
12041204

1205-
net_name: net_identifier packed_dimension_brace
1205+
net_name: net_identifier unpacked_dimension_brace
12061206
{
12071207
$$=$1;
12081208
stack_expr($$).id(ID_declarator);
@@ -1707,7 +1707,7 @@ packed_dimension_opt:
17071707

17081708
packed_dimension:
17091709
'[' const_expression TOK_COLON const_expression ']'
1710-
{ init($$, ID_array);
1710+
{ init($$, ID_verilog_packed_array);
17111711
stack_type($$).add_subtype().make_nil();
17121712
exprt &range=static_cast<exprt &>(stack_type($$).add(ID_range));
17131713
range.add_to_operands(stack_expr($2));
@@ -1717,13 +1717,14 @@ packed_dimension:
17171717

17181718
unpacked_dimension:
17191719
'[' const_expression TOK_COLON const_expression ']'
1720-
{ init($$, ID_array);
1720+
{ init($$, ID_verilog_unpacked_array);
17211721
stack_type($$).add_subtype().make_nil();
17221722
exprt &range=static_cast<exprt &>(stack_type($$).add(ID_range));
17231723
range.add_to_operands(stack_expr($2));
17241724
range.add_to_operands(stack_expr($4)); }
17251725
| '[' expression ']'
1726-
{ init($$, ID_array);
1726+
{ // starts at index 0
1727+
init($$, ID_verilog_unpacked_array);
17271728
stack_type($$).add_subtype().make_nil();
17281729
stack_type($$).set(ID_size, std::move(stack_expr($2)));
17291730
}

src/verilog/verilog_elaborate.cpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -222,7 +222,7 @@ void verilog_typecheckt::collect_symbols(const verilog_declt &decl)
222222

223223
if(declarator.type().is_nil())
224224
symbol.type = type;
225-
else if(declarator.type().id() == ID_array)
225+
else if(declarator.type().id() == ID_verilog_unpacked_array)
226226
symbol.type = array_type(declarator.type(), type);
227227
else
228228
{
@@ -401,7 +401,7 @@ void verilog_typecheckt::collect_symbols(const verilog_declt &decl)
401401

402402
if(declarator.type().is_nil())
403403
symbol.type = type;
404-
else if(declarator.type().id() == ID_array)
404+
else if(declarator.type().id() == ID_verilog_unpacked_array)
405405
symbol.type = array_type(declarator.type(), type);
406406
else
407407
{
@@ -468,7 +468,7 @@ void verilog_typecheckt::collect_symbols(const verilog_declt &decl)
468468

469469
if(declarator.type().is_nil())
470470
symbol.type = type;
471-
else if(declarator.type().id() == ID_array)
471+
else if(declarator.type().id() == ID_verilog_unpacked_array)
472472
symbol.type = array_type(declarator.type(), type);
473473
else
474474
{

src/verilog/verilog_typecheck.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -44,7 +44,7 @@ array_typet verilog_typecheckt::array_type(
4444
{
4545
// int whatnot[x:y];
4646
// 'src' is yet to be converted, but 'element_type' is already converted.
47-
PRECONDITION(src.id() == ID_array);
47+
PRECONDITION(src.id() == ID_verilog_unpacked_array);
4848

4949
// Unpacked arrays may have a range [x:y],
5050
// or a size [s], equivalent to [0:s-1]

src/verilog/verilog_typecheck_type.cpp

Lines changed: 8 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -115,7 +115,7 @@ typet verilog_typecheck_exprt::convert_type(const typet &src)
115115
result.set(ID_C_identifier, enum_type.identifier());
116116
return result.with_source_location(source_location);
117117
}
118-
else if(src.id() == ID_array)
118+
else if(src.id() == ID_verilog_packed_array)
119119
{
120120
const exprt &range=static_cast<const exprt &>(src.find(ID_range));
121121

@@ -151,7 +151,8 @@ typet verilog_typecheck_exprt::convert_type(const typet &src)
151151
}
152152
else
153153
{
154-
// we have a genuine array, and do a recursive call
154+
// We have a multi-dimensional packed array,
155+
// and do a recursive call.
155156
const exprt size=from_integer(width, integer_typet());
156157
typet s=convert_type(subtype);
157158

@@ -162,6 +163,11 @@ typet verilog_typecheck_exprt::convert_type(const typet &src)
162163
return std::move(result).with_source_location(source_location);
163164
}
164165
}
166+
else if(src.id() == ID_verilog_unpacked_array)
167+
{
168+
// not expected here -- these stick to the declarators
169+
PRECONDITION(false);
170+
}
165171
else if(src.id() == ID_verilog_type_reference)
166172
{
167173
auto &type_reference = to_verilog_type_reference(src);

0 commit comments

Comments
 (0)