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KNOWNBUG test for empty SVA sequences #1075

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Merged
merged 1 commit into from
Apr 22, 2025
Merged

KNOWNBUG test for empty SVA sequences #1075

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9 changes: 9 additions & 0 deletions regression/verilog/SVA/empty_sequence1.desc
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Original file line number Diff line number Diff line change
@@ -0,0 +1,9 @@
KNOWNBUG
empty_sequence1.sv
--bound 5
^EXIT=10$
^SIGNAL=0$
--
^warning: ignoring
--
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Would you mind adding a note as to what the problem here is?

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Done

Repetition with zero is not implemented.
14 changes: 14 additions & 0 deletions regression/verilog/SVA/empty_sequence1.sv
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module main(input clk);

reg [7:0] x = 0;

always @(posedge clk)
x<=x+1;

// The empty sequence does not match
initial p0: assert property (1[*0]);

// But can be concatenated
initial p1: assert property (1[*0] ##1 x == 0);

endmodule
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