Create issue regression tests for DRC and LVS (The-OpenROAD-Project#2039

)

+ Create 2x DRC tests and 4x LVS tests
~ Rename older tests to be more descriptive

Co-authored-by: kareefardi <[email protected]>

.gitignore

@@ -14,6 +14,7 @@ macrocell.list
 default.cvcrc
 *.log
 *.tar.gz
+abc.history
 
 # Python cache
 **/__pycache__

tests/1413-odb_remover/in.def

@@ -0,0 +1 @@
+../1007-buffer_insertion/in.def

tests/1413-odb_remover/interactive.tcl

@@ -0,0 +1,24 @@
+package require openlane;
+
+prep -design $::env(TEST_DIR) {*}$argv
+
+try_catch echo {
+    read_lef $::env(MERGED_LEF)
+    read_def $::env(DESIGN_DIR)/in.def
+    write_db $::env(DESIGN_DIR)/in.odb
+    } | openroad -exit
+
+    set ::env(CURRENT_ODB) $::env(DESIGN_DIR)/in.odb
+
+    set save_odb $::env(DESIGN_DIR)/out.odb
+
+    # Remove pins first: nets cannot be removed if they are associated with a pin
+    remove_components -input $::env(CURRENT_ODB) -output $save_odb
+    remove_pins -input $save_odb
+    remove_nets -rx {^in$} -input $save_odb
+
+    set ::env(CURRENT_ODB) $save_odb
+
+    try_catch $::env(OPENROAD_BIN) -exit -no_init -python $::env(DESIGN_DIR)/hooks/post_run.py
+
+    puts_info "Done."

tests/1506/config.json → tests/1506-config_preprocessor/config.json

@@ -17,7 +17,7 @@
     "TEST_FLOAT_CALC": "expr::2 * $CLOCK_PERIOD",
     "TEST_MALICIOUS_VAR_0": "\t\\};puts hi;[puts hi];{\"\"\"''''",
     "TEST_MALICIOUS_VAR_1": "\n\nputs hi;\n\n\u0010potato\n",
-    "TEST_INTERNAL_GLOB": "dir::../1506/src/*",
+    "TEST_INTERNAL_GLOB": "dir::../1506-config_preprocessor/src/*",
     "TEST_EXTERNAL_GLOB": "dir::../*",
     "TEST_REGEX": "x\\.y"
 }

tests/2038-drc_bad/config.json

@@ -0,0 +1,16 @@
+{
+    "DESIGN_NAME": "inverter",
+    "VERILOG_FILES": [],
+    "RUN_CTS": false,
+    "CLOCK_PORT": null,
+    "PL_RANDOM_GLB_PLACEMENT": true,
+    "FP_SIZING": "absolute",
+    "DIE_AREA": "0 0 34.5 57.12",
+    "PL_TARGET_DENSITY": 0.75,
+    "FP_PDN_AUTO_ADJUST": false,
+    "FP_PDN_VPITCH": 25,
+    "FP_PDN_HPITCH": 25,
+    "FP_PDN_VOFFSET": 5,
+    "FP_PDN_HOFFSET": 5,
+    "DIODE_INSERTION_STRATEGY": 3
+}

tests/2038-drc_bad/interactive.tcl

@@ -0,0 +1,7 @@
+package require openlane;
+
+prep -design $::env(TEST_DIR) {*}$argv
+
+set ::env(CURRENT_GDS) $::env(TEST_DIR)/inverter.gds
+
+run_magic_drc

tests/2038-drc_bad/issue_regression.py

@@ -0,0 +1,21 @@
+import os
+import subprocess
+import sys
+
+args = sys.argv[1:]
+
+run_folder = args[0]
+
+log_path = os.path.join(run_folder, "openlane.log")
+
+assert (
+    subprocess.call(
+        ["grep", "-i", "There are violations in the design after Magic DRC", log_path]
+    )
+    == 0
+), "OpenLane does not accurately report the existence of violations"
+
+assert (
+    subprocess.call(["grep", "-Pi", "Total Number of violations is \\d+", log_path])
+    == 0
+), "OpenLane does not accurately print the number of violations"

tests/2038-drc_good/config.json

@@ -0,0 +1,16 @@
+{
+    "DESIGN_NAME": "inverter",
+    "VERILOG_FILES": [],
+    "RUN_CTS": false,
+    "CLOCK_PORT": null,
+    "PL_RANDOM_GLB_PLACEMENT": true,
+    "FP_SIZING": "absolute",
+    "DIE_AREA": "0 0 34.5 57.12",
+    "PL_TARGET_DENSITY": 0.75,
+    "FP_PDN_AUTO_ADJUST": false,
+    "FP_PDN_VPITCH": 25,
+    "FP_PDN_HPITCH": 25,
+    "FP_PDN_VOFFSET": 5,
+    "FP_PDN_HOFFSET": 5,
+    "DIODE_INSERTION_STRATEGY": 3
+}

tests/2038-drc_good/interactive.tcl

@@ -0,0 +1,7 @@
+package require openlane;
+
+prep -design $::env(TEST_DIR) {*}$argv
+
+set ::env(CURRENT_GDS) $::env(TEST_DIR)/inverter.gds
+
+run_magic_drc

tests/2038-drc_good/issue_regression.py

@@ -0,0 +1,15 @@
+import os
+import subprocess
+import sys
+
+args = sys.argv[1:]
+
+run_folder = args[0]
+
+log_path = os.path.join(run_folder, "openlane.log")
+assert (
+    subprocess.call(
+        ["grep", "-i", "No DRC violations after GDS streaming out", log_path]
+    )
+    == 0
+), "OpenLane did not report the lack of DRC violations properly"

tests/2038-lvs_bad/config.json

@@ -0,0 +1,16 @@
+{
+    "DESIGN_NAME": "inverter",
+    "VERILOG_FILES": [],
+    "RUN_CTS": false,
+    "CLOCK_PORT": null,
+    "PL_RANDOM_GLB_PLACEMENT": true,
+    "FP_SIZING": "absolute",
+    "DIE_AREA": "0 0 34.5 57.12",
+    "PL_TARGET_DENSITY": 0.75,
+    "FP_PDN_AUTO_ADJUST": false,
+    "FP_PDN_VPITCH": 25,
+    "FP_PDN_HPITCH": 25,
+    "FP_PDN_VOFFSET": 5,
+    "FP_PDN_HOFFSET": 5,
+    "DIODE_INSERTION_STRATEGY": 3
+}

tests/2038-lvs_bad/interactive.tcl

@@ -0,0 +1,11 @@
+package require openlane;
+
+prep -design $::env(TEST_DIR) {*}$argv
+
+set ::env(CURRENT_DEF) $::env(TEST_DIR)/inverter.def
+set ::env(CURRENT_GDS) $::env(TEST_DIR)/inverter.gds
+set ::env(CURRENT_POWERED_NETLIST) $::env(TEST_DIR)/inverter.pnl.v
+
+set ::env(MAGIC_EXT_USE_GDS) 1
+run_magic_spice_export
+run_lvs