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- Updating the clock period of all designs in hd to reduce the spef_wns by adjusting the CLOCK_PERIOD to the value of the suggested_clock_period of a previous regression run. - Some designs were left with clock periods that produce a negative spef_wns to be used as a test of the functionality of the timing closure tools (OpenSTA, OpenPhySyn, and SPEF_EXTRACTOR)
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Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -1,4 +1,6 @@ | ||
set ::env(GLB_RT_ADJUSTMENT) 0.1 | ||
set ::env(SYNTH_STRATEGY) 3 | ||
set ::env(FP_CORE_UTIL) 20 | ||
set ::env(PL_TARGET_DENSITY) 0.15 | ||
set ::env(PL_TARGET_DENSITY) 0.15 | ||
# Suggested Clock Period: | ||
set ::env(CLOCK_PERIOD) "65.0" |
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3 changes: 3 additions & 0 deletions
3
designs/ldpc_decoder_802_3an/sky130A_sky130_fd_sc_hd_config.tcl
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Original file line number | Diff line number | Diff line change |
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@@ -1,2 +1,5 @@ | ||
set ::env(FP_CORE_UTIL) 15 | ||
set ::env(PL_TARGET_DENSITY) 0.15 | ||
|
||
# Suggested Clock Period: | ||
set ::env(CLOCK_PERIOD) "15.0" |
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Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -1,2 +1,5 @@ | ||
set ::env(FP_CORE_UTIL) 40 | ||
set ::env(PL_TARGET_DENSITY) [ expr ($::env(FP_CORE_UTIL)-10) / 100.0 ] | ||
|
||
# Suggested Clock Period: | ||
set ::env(CLOCK_PERIOD) "18.52" |
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