Update version and Changelog to go along with PR #661

efabless · Feb 13, 2025 · 09e84c1 · 09e84c1
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diff --git a/Changelog.md b/Changelog.md
@@ -14,6 +14,14 @@
 ## Documentation
 -->
 
+# 2.3.6
+
+## Steps
+
+* `Verilator.Lint`
+  * Fixed missing `VERILOG_INCLUDE_DIRS` variable, which would cause designs
+    that synthesize correctly to otherwise fail linting.
+
 # 2.3.5
 
 ## Tool Updates

diff --git a/pyproject.toml b/pyproject.toml
@@ -1,6 +1,6 @@
 [tool.poetry]
 name = "openlane"
-version = "2.3.5"
+version = "2.3.6"
 description = "An infrastructure for implementing chip design flows"
 authors = ["Efabless Corporation and Contributors <[email protected]>"]
 readme = "Readme.md"