feat: expose -keep_resize_below_overflow with PL_KEEP_RESIZE_BELOW_OV…

…ERFLOW (#655) depends on: efabless/openlane2-ci-designs#37 --------- Signed-off-by: Kareem Farid <[email protected]> Co-authored-by: Mohamed Gaber <[email protected]>
efabless · Feb 13, 2025 · 2473cd0 · 2473cd0
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Showing 7 changed files with 12 additions and 3 deletions.
diff --git a/.github/actions/setup_env/action.yml b/.github/actions/setup_env/action.yml
@@ -18,7 +18,7 @@ runs:
     - name: Check if publishing branch
       shell: bash
       run: |
-        if [[ "$BRANCH_NAME" == "main" || "$BRANCH_NAME" == version* ]]; then
+        if [[ "$BRANCH_NAME" == "main" || "$BRANCH_NAME" == "dev" || "$BRANCH_NAME" == version* ]]; then
           echo "PUBLISHING_BRANCH=1" >> $GITHUB_ENV
         fi
 

diff --git a/.github/test_sets/test_sets.yml b/.github/test_sets/test_sets.yml
@@ -16,6 +16,8 @@
     - io_placer
     - test_sram_macro
     - manual_macro_placement_test
+    - name: regs_analog_ctrl_APB
+      config_file: config.yaml
     - name: aes_user_project_wrapper
       test_name: aes_upw_new
       config_file: config.json

diff --git a/Changelog.md b/Changelog.md
@@ -78,6 +78,7 @@
 * `OpenROAD.GlobalPlacement`
 
   * Added optional variable `PL_ROUTABILITY_MAX_DENSITY_PCT`
+  * Added optional variable `PL_KEEP_RESIZE_BELOW_OVERFLOW`
 
   * Corrected `GPL_CELL_PADDING` to be an integer.
 

diff --git a/openlane/scripts/openroad/gpl.tcl b/openlane/scripts/openroad/gpl.tcl
@@ -73,6 +73,7 @@ set cell_pad_side [expr $::env(GPL_CELL_PADDING) / 2]
 lappend arg_list -pad_right $cell_pad_side
 lappend arg_list -pad_left $cell_pad_side
 lappend arg_list -init_wirelength_coef $::env(PL_WIRE_LENGTH_COEF)
+append_if_exists_argument arg_list PL_KEEP_RESIZE_BELOW_OVERFLOW -keep_resize_below_overflow
 
 log_cmd global_placement {*}$arg_list
 

diff --git a/openlane/steps/openroad.py b/openlane/steps/openroad.py
@@ -1348,6 +1348,11 @@ class _GlobalPlacement(OpenROADStep):
                 units="sites",
                 pdk=True,
             ),
+            Variable(
+                "PL_KEEP_RESIZE_BELOW_OVERFLOW",
+                Optional[Decimal],
+                "Only applicable when PL_TIME_DRIVEN is enabled. When the overflow is below the set value, timing-driven iterations will retain the resizer changes instead of reverting them. Allowed values are 0 to 1. If not set, a nonzero default value from OpenROAD will be used",
+            ),
         ]
     )
 

diff --git a/pyproject.toml b/pyproject.toml
@@ -1,6 +1,6 @@
 [tool.poetry]
 name = "openlane"
-version = "3.0.0.dev13"
+version = "3.0.0.dev14"
 description = "An infrastructure for implementing chip design flows"
 authors = ["Efabless Corporation and Contributors <[email protected]>"]
 readme = "Readme.md"

diff --git a/test/designs b/test/designs
+58 −0		regs_analog_ctrl_APB/base.sdc
+51 −0		regs_analog_ctrl_APB/config.yaml
+301 −0		regs_analog_ctrl_APB/pin_order.cfg
+1,063 −0		regs_analog_ctrl_APB/regs_analog_ctrl.v
+1,816 −0		regs_analog_ctrl_APB/regs_analog_ctrl_APB.v
+27 −0		regs_analog_ctrl_APB/signoff.sdc