Add intercore communication example for STM32H755CM4 and CM7

[Ragarnoy]

This pull request introduces intercore communication examples for the STM32H755CM4 and CM7.

This runs fine in dev.
A lot of inlining has to be disabled for this to work in release, otherwise the following symptoms may appear:

• Second core does not do anything
• Second core blinks red led (heartbeat) but never sees the shared data being updated (write is being cached)
• TBA

Expected behaviour of the example

1. CM7 Main Loop

   Counter increment: every 100 ms, CM7 does counter.store(counter+1).

   Green LED toggle: when counter % 10 == 0 (i.e. every 1 s), CM7 flips the green‐bit in led_states.

   Yellow LED toggle: when counter % 30 == 0 (i.e. every 3 s), CM7 flips the yellow‐bit.

2. CM4 Observer Task

   Heartbeat Task: CM4’s blink_heartbeat toggles the red LED every 500 ms, independent of shared memory.

   Shared‐LED Sync: In its main loop (polled every 10 ms), CM4:

    Reads led_states and counter atomically.
   
    If the green‐bit changed, it drives its green GPIO high/low.
   
    If the yellow‐bit changed, it drives its yellow GPIO high/low.
   
    Logs any change to the console.
   

3. Visual Result

   Red LED blinking steadily at 2 Hz (heartbeat).

   Green LED blinking at 0.5 Hz (1 s on/off).

   Yellow LED blinking at ≈0.166 Hz (3 s on/off), phase-aligned to the green toggles.

When detaching the RTT logging, the first core is halted, but the red led will keep blinking since it's driven by the second core.

[Ragarnoy]

@diondokter Asking for your point of view on this since you did all of the work for the dual core H7 on embassy

[diondokter]

In a bunch of places you do this fence after an atomic operation. I don't think this is necessary (though I could be wrong)