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Bump mlir-air to c78cf3fb0c8c147d519692952995ba7413604c16
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erwei-xilinx committed Jan 9, 2025
1 parent f519ca2 commit b89e0c2
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Showing 3 changed files with 27 additions and 3 deletions.
19 changes: 19 additions & 0 deletions compiler/plugins/target/AMD-AIE/air/CMakeLists.txt
Original file line number Diff line number Diff line change
Expand Up @@ -329,6 +329,25 @@ iree_cc_library(
MLIRSupport
)

replace_string_in_file(
${IREE_MLIR_AIR_SOURCE_DIR}/lib/Transform/AIRDependencyScheduleOpt.cpp
"aie/Dialect/AIE/IR" "aie")
replace_string_in_file(
${IREE_MLIR_AIR_SOURCE_DIR}/lib/Transform/AIRDependencyScheduleOpt.cpp
"aie/Dialect/AIEX/IR" "aie")
replace_string_in_file(
${IREE_MLIR_AIR_SOURCE_DIR}/lib/Transform/AIRDependencyScheduleOpt.cpp
"AIE::getTargetModel(*device)"
"getDeviceModel(*device)")
replace_string_in_file(
${IREE_MLIR_AIR_SOURCE_DIR}/lib/Transform/AIRDependencyScheduleOpt.cpp
"isa<AIE::AIE1TargetModel>(getDeviceModel(*device))"
"false")
replace_string_in_file(
${IREE_MLIR_AIR_SOURCE_DIR}/lib/Transform/AIRDependencyScheduleOpt.cpp
"isa<AIE::AIE1TargetModel>(getDeviceModel(*device))"
"true")

###############################################################################
# AIR Passes
###############################################################################
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Original file line number Diff line number Diff line change
Expand Up @@ -809,8 +809,7 @@ void addMLIRAIRLoweringPasses(OpPassManager &passManager, AMDAIEDevice device,
passManager.addPass(createCSEPass());
passManager.addPass(createCanonicalizerPass());
passManager.addPass(createCSEPass());
passManager.addNestedPass<func::FuncOp>(
xilinx::air::createAIRSegmentLoopFusion());
passManager.addNestedPass<func::FuncOp>(xilinx::air::createAIRLoopFusion());

passManager.addPass(
xilinx::air::createAIRLabelScfForLoopForPingPongPattern());
Expand Down Expand Up @@ -863,6 +862,12 @@ void addMLIRAIRLoweringPasses(OpPassManager &passManager, AMDAIEDevice device,
}
passManager.addPass(createCanonicalizerPass());
passManager.addPass(xilinx::air::createAIRLoweringPass());
{
xilinx::air::AIROptimizeShimDMABDsOptions options;
options.clDevice = stringifyEnum(device);
passManager.addNestedPass<func::FuncOp>(
xilinx::air::createAIROptimizeShimDMABDs(options));
}
{
xilinx::air::AffineLoopOptPassOptions options;
// tile_sizes contains a list of N tiling factors for the N innermost loop
Expand Down
2 changes: 1 addition & 1 deletion third_party/mlir-air
Submodule mlir-air updated 96 files
+0 −20 docs/README.md
+20 −10 mlir/include/air/Conversion/AIRToAIESchedulingUtils.h
+65 −0 mlir/include/air/Dialect/AIR/AIR.td
+12 −0 mlir/include/air/Dialect/AIR/AIROpBase.td
+20 −1 mlir/include/air/Transform/AIRDependencyScheduleOpt.h
+4 −1 mlir/include/air/Transform/PassDetail.h
+46 −2 mlir/include/air/Transform/Passes.td
+7 −4 mlir/include/air/Util/Dependency.h
+17 −4 mlir/include/air/Util/Util.h
+1 −0 mlir/lib/Conversion/AIRLoweringPass.cpp
+140 −172 mlir/lib/Conversion/AIRRtToNpuPass.cpp
+354 −240 mlir/lib/Conversion/AIRToAIEPass.cpp
+224 −85 mlir/lib/Conversion/AIRToAIESchedulingUtils.cpp
+3 −3 mlir/lib/Conversion/ConvertToAIRPass.cpp
+178 −18 mlir/lib/Dialect/AIR/IR/AIRDialect.cpp
+99 −140 mlir/lib/Transform/AIRDependency.cpp
+1,764 −1,043 mlir/lib/Transform/AIRDependencyScheduleOpt.cpp
+232 −193 mlir/lib/Transform/AIRDmaToChannel.cpp
+2 −10 mlir/lib/Transform/AIRLowerLinalgTensors.cpp
+57 −29 mlir/lib/Transform/AIRMiscPasses.cpp
+197 −142 mlir/lib/Util/Dependency.cpp
+11 −10 mlir/lib/Util/Outliner.cpp
+2 −2 mlir/lib/Util/Runner.cpp
+117 −66 mlir/lib/Util/Util.cpp
+1 −0 mlir/test/Conversion/AIRLowering/air_to_npu.mlir
+1 −1 mlir/test/Conversion/AIRRtToNpu/airrt_to_npu.mlir
+2 −2 mlir/test/Conversion/AIRToAIE/air_channel_to_locks_core_to_core.mlir
+9 −14 mlir/test/Conversion/AIRToAIE/air_channel_to_locks_ping_pong.mlir
+16 −16 mlir/test/Conversion/AIRToAIE/air_shimcpy_to_aie.mlir
+18 −18 mlir/test/Conversion/AIRToAIE/air_shimcpy_to_aie2_with_shim_dma_bds.mlir
+10 −10 mlir/test/Conversion/AIRToAIE/air_shimcpy_to_aie_with_shim_dma_bds.mlir
+146 −28 mlir/test/Conversion/AIRToAIE/air_shimcpy_to_npu.mlir
+8 −8 mlir/test/Conversion/AIRToAIE/air_to_npu_add_one.mlir
+4 −4 mlir/test/Conversion/AIRToAIE/async_gemm_w_pingpong_to_locks_aie2.mlir
+4 −4 mlir/test/Conversion/AIRToAIE/async_gemm_w_pingpong_to_locks_npu.mlir
+255 −6 mlir/test/Conversion/AIRToAIE/emit_lock.mlir
+131 −6 mlir/test/Conversion/ConvertToAIR/dma_to_channel_async.mlir
+0 −83 mlir/test/Conversion/ConvertToAIR/dma_to_channel_nested_for_in_partition.mlir
+304 −0 mlir/test/Conversion/ConvertToAIR/dma_to_channel_nested_for_in_segment.mlir
+291 −0 mlir/test/Dialect/AIR/air_canonicalize.mlir
+5 −5 mlir/test/Transform/AIRAutomaticTiling/air_automatic_tiling_pass.mlir
+74 −3 mlir/test/Transform/AIRDependency/air_channel.mlir
+394 −0 mlir/test/Transform/AIRDependencyScheduleOpt/fuse_alloc_dealloc.mlir
+274 −0 mlir/test/Transform/AIRDependencyScheduleOpt/fuse_channels.mlir
+1 −1 mlir/test/Transform/AIRDependencyScheduleOpt/hoist_non_pingpong_ops.mlir
+301 −10 mlir/test/Transform/AIRDependencyScheduleOpt/isolate_async_dma_loop_nest.mlir
+150 −1 mlir/test/Transform/AIRDependencyScheduleOpt/loop_fusion.mlir
+235 −0 mlir/test/Transform/AIRDependencyScheduleOpt/opt_shim_dma_bds.mlir
+53 −0 mlir/test/Transform/AIRDependencyScheduleOpt/shrink_memref_sizes_by_access.mlir
+66 −54 mlir/test/Transform/AIRDependencyScheduleOpt/specialize-channel-wrap-and-stride.mlir
+5 −5 mlir/test/Transform/AIRLinalgCodegen/air_linalg_codegen_matmul.mlir
+5 −5 mlir/test/Transform/AIRLoopMerging/air_loop_merging_pass.mlir
+5 −5 mlir/test/Transform/AIRLoopPermutation/air_loop_permutation_pass.mlir
+258 −0 mlir/test/Transform/AIRMiscPasses/air_split_l2_memref.mlir
+5 −5 mlir/test/Transform/AIRRegularizeLoop/air_regularize_loop_pass.mlir
+2 −2 mlir/test/Transform/AffineLoopOpt/affine_opt_tile_add1.mlir
+6 −0 python/air/backend/xrt_runner.py
+5 −4 python/air/compiler/aircc/main.py
+1 −0 test/xrt/01_air_to_npu/aie.py
+1 −0 test/xrt/04_gemm_w_pack/aie.py
+1 −0 test/xrt/06_add_shim_bf16/gen.py
+1 −0 test/xrt/07_extern_linalg/gen.py
+1 −0 test/xrt/08_gemm_extern_vec/aie.py
+1 −0 test/xrt/09_gemm_extern_vec_4x4/aie.py
+1 −0 test/xrt/10_gemm_peeling_extern_vec/aie.py
+1 −0 test/xrt/11_gemm_bias_fusion/aie.py
+18 −20 test/xrt/12_matmul_transform_1x4_bf16/gen.py
+11 −10 test/xrt/12_matmul_transform_1x4_bf16/kernel.cpp
+0 −1 test/xrt/12_matmul_transform_1x4_bf16/run.lit
+3 −3 test/xrt/12_matmul_transform_1x4_bf16/run.py
+6 −5 test/xrt/12_matmul_transform_1x4_bf16/transform.mlir
+1 −0 test/xrt/13_conv2d_i32/aie.py
+1 −0 test/xrt/14_conv2d_i8_extern_vec/aie.py
+1 −0 test/xrt/15_gemm_peeling_extern_vec_4x4_bf16/aie.py
+1 −0 test/xrt/16_gemm_peeling_extern_vec_4x4_bf16_packet/aie.py
+1 −0 test/xrt/17_gemm_8x16_transform_vec_4x4/gen.py
+1 −0 test/xrt/18_matmul_8x16_shim_transform_bf16/gen.py
+1 −0 test/xrt/19_matmul_8x16_core_transform_bf16/gen.py
+1 −0 test/xrt/20_batch_matmul_i32/aie.py
+1 −0 test/xrt/21_conv2d_depthwise_i32/aie.py
+1 −0 test/xrt/22_conv2d_stride2_i32/aie.py
+1 −0 test/xrt/23_ctrlpkt_config/aie.py
+1 −0 test/xrt/24_ctrlpkt_config_2gemms_4x4/aie.py
+1 −0 test/xrt/24_ctrlpkt_config_2gemms_4x4/aie2.py
+1 −0 test/xrt/25_batch_matmul_bf16/aie.py
+1 −0 test/xrt/26_vecmat_i8/aie.py
+1 −0 test/xrt/27_gemm_peeling_extern_vec_4x4_i32/aie.py
+237 −0 test/xrt/28_gemm_loop_nest_bf16/aie.py
+290 −0 test/xrt/28_gemm_loop_nest_bf16/matrix_multiplication.h
+340 −0 test/xrt/28_gemm_loop_nest_bf16/mm.cc
+10 −0 test/xrt/28_gemm_loop_nest_bf16/run.lit
+215 −0 test/xrt/28_gemm_loop_nest_bf16/test.cpp
+33 −0 test/xrt/28_gemm_loop_nest_bf16/zero.cc
+2 −0 tools/air-opt/air-opt.cpp
+1 −1 utils/clone-llvm.sh
+1 −1 utils/clone-mlir-aie.sh

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