Bump aie-rt (nod-ai#970)

This PR moves aie-rt forward about 5 months. Our on-the-fly string matching fix in iree_aie_rt is dropped because Xilinx/aie-rt#4 is fixed. The other changes appear minor.
erwei-xilinx · Dec 9, 2024 · c1a63ed · c1a63ed
1 parent 31b2cdb
commit c1a63ed
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diff --git a/cmake/iree_aie_rt.cmake b/cmake/iree_aie_rt.cmake
@@ -46,202 +46,6 @@ include(${_aie_rt_source_dir}/fal/cmake/collect.cmake)
 set(XAIENGINE_BUILD_SHARED OFF CACHE BOOL "" FORCE)
 add_subdirectory(${_aie_rt_source_dir}/driver/src iree_aie_runtime)
 
-# https://github.com/Xilinx/aie-rt/issues/4
-set(_incorrect_port_map "
-static const XAie_StrmSwPortMap AieMlMemTileStrmSwSlavePortMap[] =
-{
-	{
-		/* PhyPort 0 */
-		.PortType = DMA,
-		.PortNum = 0,
-	},
-	{
-		/* PhyPort 1 */
-		.PortType = DMA,
-		.PortNum = 1,
-	},
-	{
-		/* PhyPort 2 */
-		.PortType = DMA,
-		.PortNum = 2,
-	},
-	{
-		/* PhyPort 3 */
-		.PortType = DMA,
-		.PortNum = 3,
-	},
-	{
-		/* PhyPort 4 */
-		.PortType = DMA,
-		.PortNum = 4,
-	},
-	{
-		/* PhyPort 5 */
-		.PortType = DMA,
-		.PortNum = 5,
-	},
-	{
-		/* PhyPort 6 */
-		.PortType = CTRL,
-		.PortNum = 0,
-	},
-	{
-		/* PhyPort 7 */
-		.PortType = SOUTH,
-		.PortNum = 0,
-	},
-	{
-		/* PhyPort 8 */
-		.PortType = SOUTH,
-		.PortNum = 1,
-	},
-	{
-		/* PhyPort 9 */
-		.PortType = SOUTH,
-		.PortNum = 2,
-	},
-	{
-		/* PhyPort 10 */
-		.PortType = SOUTH,
-		.PortNum = 3,
-	},
-	{
-		/* PhyPort 11 */
-		.PortType = NORTH,
-		.PortNum = 0,
-	},
-	{
-		/* PhyPort 12 */
-		.PortType = NORTH,
-		.PortNum = 1,
-	},
-	{
-		/* PhyPort 13 */
-		.PortType = NORTH,
-		.PortNum = 2,
-	},
-	{
-		/* PhyPort 14 */
-		.PortType = NORTH,
-		.PortNum = 3,
-	},
-	{
-		/* PhyPort 15 */
-		.PortType = NORTH,
-		.PortNum = 4,
-	},
-	{
-		/* PhyPort 16 */
-		.PortType = NORTH,
-		.PortNum = 5,
-	},
-	{
-		/* PhyPort 17 */
-		.PortType = TRACE,
-		.PortNum = 0,
-	},
-};
-")
-
-set(_correct_port_map "
-static const XAie_StrmSwPortMap AieMlMemTileStrmSwSlavePortMap[] = {
-    {
-        /* PhyPort 0 */
-        .PortType = DMA,
-        .PortNum = 0,
-    },
-    {
-        /* PhyPort 1 */
-        .PortType = DMA,
-        .PortNum = 1,
-    },
-    {
-        /* PhyPort 2 */
-        .PortType = DMA,
-        .PortNum = 2,
-    },
-    {
-        /* PhyPort 3 */
-        .PortType = DMA,
-        .PortNum = 3,
-    },
-    {
-        /* PhyPort 4 */
-        .PortType = DMA,
-        .PortNum = 4,
-    },
-    {
-        /* PhyPort 5 */
-        .PortType = DMA,
-        .PortNum = 5,
-    },
-    {
-        /* PhyPort 6 */
-        .PortType = CTRL,
-        .PortNum = 0,
-    },
-    {
-        /* PhyPort 7 */
-        .PortType = SOUTH,
-        .PortNum = 0,
-    },
-    {
-        /* PhyPort 8 */
-        .PortType = SOUTH,
-        .PortNum = 1,
-    },
-    {
-        /* PhyPort 9 */
-        .PortType = SOUTH,
-        .PortNum = 2,
-    },
-    {
-        /* PhyPort 10 */
-        .PortType = SOUTH,
-        .PortNum = 3,
-    },
-    {
-        /* PhyPort 11 */
-        .PortType = SOUTH,
-        .PortNum = 4,
-    },
-    {
-        /* PhyPort 12 */
-        .PortType = SOUTH,
-        .PortNum = 5,
-    },
-    {
-        /* PhyPort 13 */
-        .PortType = NORTH,
-        .PortNum = 0,
-    },
-    {
-        /* PhyPort 14 */
-        .PortType = NORTH,
-        .PortNum = 1,
-    },
-    {
-        /* PhyPort 15 */
-        .PortType = NORTH,
-        .PortNum = 2,
-    },
-    {
-        /* PhyPort 16 */
-        .PortType = NORTH,
-        .PortNum = 3,
-    },
-    {
-        /* PhyPort 17 */
-        .PortType = TRACE,
-        .PortNum = 0,
-    },
-};
-")
-
-replace_string_in_file(
-  ${_aie_rt_source_dir}/driver/src/global/xaie2ipugbl_reginit.c
-  "${_incorrect_port_map}" "${_correct_port_map}")
-
 get_target_property(_aie_runtime_compile_options xaiengine COMPILE_OPTIONS)
 list(REMOVE_ITEM _aie_runtime_compile_options -D__AIEBAREMETAL__)
 

diff --git a/runtime/src/iree-amd-aie/aie_runtime/iree_aie_runtime.cc b/runtime/src/iree-amd-aie/aie_runtime/iree_aie_runtime.cc
@@ -881,9 +881,13 @@ std::string to_string(const XAie_TxnOpcode &value) {
     STRINGIFY_ENUM_CASE(XAie_TxnOpcode::XAIE_IO_BLOCKSET)
     STRINGIFY_ENUM_CASE(XAie_TxnOpcode::XAIE_IO_MASKWRITE)
     STRINGIFY_ENUM_CASE(XAie_TxnOpcode::XAIE_IO_MASKPOLL)
+    STRINGIFY_ENUM_CASE(XAie_TxnOpcode::XAIE_IO_NOOP)
+    STRINGIFY_ENUM_CASE(XAie_TxnOpcode::XAIE_IO_PREEMPT)
+    STRINGIFY_ENUM_CASE(XAie_TxnOpcode::XAIE_IO_MASKPOLL_BUSY)
+    STRINGIFY_ENUM_CASE(XAie_TxnOpcode::XAIE_IO_LOADPDI)
+    STRINGIFY_ENUM_CASE(XAie_TxnOpcode::XAIE_IO_LOAD_PM_START)
     STRINGIFY_ENUM_CASE(XAie_TxnOpcode::XAIE_CONFIG_SHIMDMA_BD)
     STRINGIFY_ENUM_CASE(XAie_TxnOpcode::XAIE_CONFIG_SHIMDMA_DMABUF_BD)
-    //    STRINGIFY_ENUM_CASE(XAie_TxnOpcode::XAIE_IO_CUSTOM_OP_BEGIN)
     STRINGIFY_ENUM_CASE(XAie_TxnOpcode::XAIE_IO_CUSTOM_OP_TCT)
     STRINGIFY_ENUM_CASE(XAie_TxnOpcode::XAIE_IO_CUSTOM_OP_DDR_PATCH)
     STRINGIFY_ENUM_CASE(XAie_TxnOpcode::XAIE_IO_CUSTOM_OP_READ_REGS)

diff --git a/runtime/src/iree-amd-aie/aie_runtime/iree_aie_runtime.h b/runtime/src/iree-amd-aie/aie_runtime/iree_aie_runtime.h
@@ -8,8 +8,6 @@
 #define IREE_AIE_RUNTIME_H
 
 #include <optional>
-#include <ostream>
-#include <sstream>
 #include <tuple>
 #include <type_traits>
 
@@ -166,6 +164,11 @@ enum class XAie_TxnOpcode : uint8_t {
   XAIE_IO_BLOCKSET,
   XAIE_IO_MASKWRITE,
   XAIE_IO_MASKPOLL,
+  XAIE_IO_NOOP,
+  XAIE_IO_PREEMPT,
+  XAIE_IO_MASKPOLL_BUSY,
+  XAIE_IO_LOADPDI,
+  XAIE_IO_LOAD_PM_START,
   XAIE_CONFIG_SHIMDMA_BD,
   XAIE_CONFIG_SHIMDMA_DMABUF_BD,
   XAIE_IO_CUSTOM_OP_BEGIN = ::XAie_TxnOpcode::XAIE_IO_CUSTOM_OP_BEGIN,

diff --git a/third_party/aie-rt b/third_party/aie-rt