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Rebase
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playfulFence committed Feb 6, 2025
1 parent 1d2a206 commit 1f078db
Showing 1 changed file with 8 additions and 3 deletions.
11 changes: 8 additions & 3 deletions esp-hal/src/uart.rs
Original file line number Diff line number Diff line change
Expand Up @@ -2448,7 +2448,7 @@ impl Info {
sync_regs(self.regs());
}

fn change_baud(&self, config: &Config) {
fn change_baud(&self, config: &Config) -> Result<(), ConfigError> {
let clocks = Clocks::get();
let clk = match config.clock_source {
ClockSource::Apb => clocks.apb_clock.as_hz(),
Expand Down Expand Up @@ -2523,7 +2523,7 @@ impl Info {

self.sync_regs();

let actual_baud = self.get_baudrate(clk);
self.verify_baudrate(clk, config)?;

Ok(())
}
Expand Down Expand Up @@ -2598,7 +2598,12 @@ impl Info {
let actual_baud = (clk << 4) / ((((clkdiv as u32) << 4) | clkdiv_frag) * (sclk_div_num + 1));
} else { // esp32c6, esp32h2
let pcr = crate::peripherals::PCR::regs();
let sclk_div_num = pcr.uart0_sclk_conf().read().uart0_sclk_div_num().bits() as u32;
let conf = if self.is_instance(unsafe { crate::peripherals::UART0::steal() }) {
pcr.uart(0).clk_conf()
} else {
pcr.uart(1).clk_conf()
};
let sclk_div_num = conf.read().sclk_div_num().bits() as u32;
let actual_baud = (clk << 4) / ((((clkdiv as u32) << 4) | clkdiv_frag) * (sclk_div_num + 1));
}
};
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