RISCV CPU

An attempt at building a simple RISCV CPU in verilog. Currently my CPU implements the RV32I ISA without FENCE/ECALL/EBREAK instructions. The design is very much based on David and Sarah Harris' book "Digital Design and Computer Architecture (RISC-V Edition)".

FPGA

The board used in this project is a Tang Nano 9K with a GW1NR-LV9QN88PC6/I5 FPGA. There is a crystal clock onboard running at 27 MHz.

Build

• make all alias for make simulate.
• make rom to build rom.
• make objdump to disassemble rom.
• make size to display size information of rom.
• make testvec to generate testvectors.
• make simulate to run testbenches.
• make wave to view waveform of cpu testbench in gtkwave.
• make bitstream to generate bitstream.
• make upload to upload bitstream to fpga.
• make flash to flash bitstream to fpga.
• make clean to clean build folder.

Project Structure

riscv_cpu
  |-> build         # build folder
  |-> debug
    |-> cpu.gtkw    # template for gtkwave
  |-> prog          # program that gets compiled to run on cpu
    |-> include
    |-> src
    |-> link.ld
    |-> Makefile
  |-> res           # various resources
  |-> rtl           # rtl sources (verilog files)
    |-> cst         # constraints file for fpga
    |-> include
    |-> src
    |-> Makefile
  |-> sim
    |-> gentestvec  # programs to generate testvectors for testbenches
      |-> src
      |-> Makefile
    |-> testbenches # testbench sources
      |-> src
      |-> Makefile
  |-> Makefile
  |-> README.md

Tools

Simulation

• clang for compiling testvector generator sources
• iverilog for building simulation
• vvp for running simulation

ROM

• riscv64 toolchain for building prog source files, although here used for compiling for riscv32

Synthesis

• yosys for synthesis
• nextpnr-himbaechel for place and route
• gowin_pack for generating bitstream
• openFPGALoader for uploading bitstream to FPGA

Debugging

• gtkwave for viewing waveforms
• (openocd for debugging)

Currently Supported Instructions

• R-type: add, sub, and, or, xor, sll, srl, sra, slt, sltu
• I-type: addi, andi, ori, xori, slti, sltiu, slli, srli, srai, lw, lh, lhu, lb, lbu
• S-type: sw, sh, sb
• B-type: beq, bne, blt, bge, bltu, bgeu
• U-type: lui, auipc
• J-type: jal, jalr

Resources

• RISC-V ISA
• Digital Design and Computer Architecture by David and Sarah Harris
• DDCA Course by SAFARI Research Group, ETH Zürich
• Computer Organization and Design by David Patterson
• Operating Systems: Three Easy Pieces by Remzi and Andrea Arpaci-Dusseau
• Example RISCV Cores
• godbolt (compiler explorer)
• DDCA Notes

Design

Microarchitecture (RISC-V multicycle rv32i without FENCE/ECALL/EBREAK)

Control Unit FSM

Memory Layout

ALU

Waveform Example

Here we can see the waveforms of various internal signal of the CPU, executing the following instructions:

  addi  t0, zero, 5
  addi  t1, zero, 3
  add   t2, t0,   t1

RISC-V

RV32I ISA

Registers