feat(phd-phase2-stubkill-2-9): expand App.I XDC pin map — reading guide / bank topology / R7 hooks

[gHashTag]

Closes #265\n\n## Phase 2 STUB-KILL · task 2.9 — App.I XDC pin map expansion

Closes trios#380 Phase 2 manifest task 2.9 (line 65).

Pre/post

Metric	Pre	Post
docs/phd/appendix/I-xdc-pin-map.tex	4,435 B / 141 lines	16,227 B / 378 lines
\label sites in I	1	14
Total monograph \label sites	1170	1184 (0 dup, 0 dangling)
\begin/\end env balance	18/18	18/18

What changed

• §I.0 Reading guide — XDC primer for non-FPGA readers (PACKAGE_PIN / IOSTANDARD / timing decomposition)
• §I.7 I/O bank topology — pins grouped by bank-14 / bank-15; UART bank inference (D20/E19) marked audit-pending per R5
• §I.8 Timing constraint rationale — 20 ns clock derivation, 92 MHz PLL multiplier 9.2/5, false-path semantics
• §I.9 Schematic provenance — QMTech rev 2.1 + UG475; UART one-degree indirection flagged
• §I.10 Reproduction protocol — cargo run -p trinity-fpga -- synthesize (R1: no .sh); deterministic synth flags; SHA-256 cross-link to App.M
• §I.11 Open issues — 4 honest open items (UART bank, FPGA-side JTAG blank-by-design, XC7A200T full-die, multi-board parity)
• §I.12 Falsification hooks — R7 pre-registered: synthesis fail / IOSTANDARD violation / SHA-256 drift / negative WNS

Preserved verbatim

All 11 pin coordinates (U18, D20, E19, R14, P14, N16, M16, IO18-23, IO35), all \begin{verbatim} XDC blocks, IDCODE 0x13631093, STAT 0x401079FC, 50 MHz → 92 MHz PLL chain.

R-rule compliance

• R1 ✅ zero .py / .sh blocks
• R5 ✅ UART bank, XC7A200T full-die pinout, multi-board parity → audit-pending
• R7 ✅ 4 falsification hooks pre-registered
• R10 ✅ single atomic commit fede810

Stack

• base: feat/phd-phase2-stubkill-2-10 (PR #612, tip 0066a58)
• this: feat/phd-phase2-stubkill-2-9 tip fede810

🌻 Phase 2 STUB-KILL: 9/10 lanes done after this merge. Remaining: task 2.7 (App.F FPGA bitstream + SHA-256).

φ² + φ⁻² = 3 · DOI 10.5281/zenodo.19227877 · defense 2026-06-15

(Re-opened from auto-closed #613 after chained-base-branch deletion in PhD batch-merge.)