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ggml : implement REGLU/GEGLU/SWIGLU ops #14158
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76c9bc1
implement unary REGLU/GEGLU/SWIGLU cpu ops
CISC 5a490f0
relax constraints
CISC 56c7993
duplicate shape of source
CISC 21c4963
fix ggml_vec_geglu_f16
CISC bb2fda7
special case gated ops
CISC a1a7b6d
implement unary REGLU/GEGLU/SWIGLU cuda ops
CISC f8c2080
tighten constraints again
CISC a341aa3
refactor into GGML_GLU_OP
CISC d9ddeb9
metal : add glu kernels
ggerganov cfa9c7a
add CUDA_GLU_BLOCK_SIZE [no ci]
CISC 70e8b48
more constraints and use 64bit ints
CISC f8705a2
64bit multiplication [no ci]
CISC 0b2703f
implement swapped variants (cpu/cuda)
CISC d593429
update comment [no ci]
CISC 34d1aed
Vulkan: Add GLU ops and shaders
0cc4m a9aedf4
SYCL: Implement fused kernel GEGLU, SWIGLU and REGLU for single up+gate
qnixsynapse 35dacd1
ggml : implement GLU for split up/gate (#14181)
CISC a234e09
GGML: increase OP count in assertion
qnixsynapse ab46d11
Refactor: Optimize SYCL element-wise operations with unary function i…
qnixsynapse 650d398
vulkan: Increase workgroup size for GLU, for performance (#14345)
jeffbolznv 8bca3e2
merge fix
CISC a6b641e
Merge branch 'master' into cisc/unary-reglu-geglu-swiglu
CISC 9054f1a
metal : add support for split and swap
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