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mczyz-antmicromczyz-antmicro
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Format with dslx_fmt
Signed-off-by: Michal Czyz <[email protected]>
1 parent ab964ce commit 89c11af

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5 files changed

+266
-372
lines changed

5 files changed

+266
-372
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‎xls/modules/axi4/dma/axi_csr.x

Lines changed: 83 additions & 111 deletions
Original file line numberDiff line numberDiff line change
@@ -55,11 +55,11 @@ pub struct axi_r_t<ID_W: u32, DATA_W: u32> {
5555
rlast: uN[1],
5656
}
5757

58-
pub struct axi_csr_state <ADDR_W: u32, DATA_W: u32>{
58+
pub struct axi_csr_state<ADDR_W: u32, DATA_W: u32> {
5959
waddr: uN[ADDR_W],
6060
wdata: uN[DATA_W],
6161
raddr: uN[ADDR_W],
62-
rdata: uN[DATA_W]
62+
rdata: uN[DATA_W],
6363
}
6464

6565
// AXI4 subordinate receives AXI4 transactions and translates them into simple
@@ -68,62 +68,51 @@ proc axi_csr<ID_W: u32, ADDR_W: u32, DATA_W: u32, STRB_W: u32, REGS_N: u32> {
6868
aw_ch: chan<axi_aw_t<ID_W, ADDR_W>> in;
6969
w_ch: chan<axi_w_t<DATA_W, STRB_W>> in;
7070
b_ch: chan<axi_b_t<ID_W>> out;
71-
ar_ch: chan<axi_ar_t<ID_W, ADDR_W>>in;
72-
r_ch: chan<axi_r_t<ID_W, DATA_W>>out;
73-
74-
read_req: chan<csr::ReadReq<ADDR_W>> out;
75-
read_resp: chan<csr::ReadResp<DATA_W>> in;
76-
write_req: chan<csr::WriteReq<ADDR_W, DATA_W>> out;
71+
ar_ch: chan<axi_ar_t<ID_W, ADDR_W>> in;
72+
r_ch: chan<axi_r_t<ID_W, DATA_W>> out;
73+
read_req: chan<csr::ReadReq<ADDR_W>> out;
74+
read_resp: chan<csr::ReadResp<DATA_W>> in;
75+
write_req: chan<csr::WriteReq<ADDR_W, DATA_W>> out;
7776
write_resp: chan<csr::WriteResp> in;
78-
all_csr: chan<csr::AllCSR<DATA_W,REGS_N>> out;
79-
80-
config(aw_ch: chan<axi_aw_t<ID_W, ADDR_W>> in,
81-
w_ch: chan<axi_w_t<DATA_W, STRB_W>> in,
82-
b_ch: chan<axi_b_t<ID_W>> out,
83-
ar_ch: chan<axi_ar_t<ID_W, ADDR_W>>in,
84-
r_ch: chan<axi_r_t<ID_W, DATA_W>>out,
85-
all_csr: chan<csr::AllCSR<DATA_W,REGS_N>> out
86-
) {
77+
all_csr: chan<csr::AllCSR<DATA_W, REGS_N>> out;
78+
79+
config(aw_ch: chan<axi_aw_t<ID_W, ADDR_W>> in, w_ch: chan<axi_w_t<DATA_W, STRB_W>> in, b_ch
80+
:
81+
chan<axi_b_t<ID_W>> out,
82+
ar_ch: chan<axi_ar_t<ID_W, ADDR_W>> in, r_ch: chan<axi_r_t<ID_W, DATA_W>> out, all_csr
83+
:
84+
chan<csr::AllCSR<DATA_W, REGS_N>> out) {
8785
let (read_req_s, read_req_r) = chan<csr::ReadReq<ADDR_W>>;
8886
let (read_resp_s, read_resp_r) = chan<csr::ReadResp<DATA_W>>;
8987
let (write_req_s, write_req_r) = chan<csr::WriteReq<ADDR_W, DATA_W>>;
9088
let (write_resp_s, write_resp_r) = chan<csr::WriteResp>;
9189

92-
spawn csr::CSR<ADDR_W, DATA_W, REGS_N>(read_req_r, read_resp_s, write_req_r, write_resp_s, all_csr);
90+
spawn csr::CSR<ADDR_W, DATA_W, REGS_N>(
91+
read_req_r, read_resp_s, write_req_r, write_resp_s, all_csr);
9392
(
94-
aw_ch, w_ch, b_ch, ar_ch, r_ch,
95-
read_req_s, read_resp_r, write_req_s,write_resp_r,
96-
all_csr
93+
aw_ch, w_ch, b_ch, ar_ch, r_ch, read_req_s, read_resp_r, write_req_s, write_resp_r,
94+
all_csr,
9795
)
9896
}
9997

100-
init { axi_csr_state<ADDR_W, DATA_W>{
101-
waddr: uN[ADDR_W]:0,
102-
wdata: uN[DATA_W]:0,
103-
raddr: uN[ADDR_W]:0,
104-
rdata: uN[DATA_W]:0
105-
} }
98+
init {
99+
axi_csr_state<ADDR_W, DATA_W> {
100+
waddr: uN[ADDR_W]:0, wdata: uN[DATA_W]:0, raddr: uN[ADDR_W]:0, rdata: uN[DATA_W]:0
101+
}
102+
}
106103

107104
next(tok: token, state: axi_csr_state<ADDR_W, DATA_W>) {
108105
// AW Channel Handler
109106
let (tok, aw_payload, aw_valid) = recv_non_blocking(tok, aw_ch, zero!<axi_aw_t>());
110-
let w_addr = if( aw_valid ) {
111-
aw_payload.awaddr
112-
} else {
113-
state.waddr
114-
};
107+
let w_addr = if aw_valid { aw_payload.awaddr } else { state.waddr };
115108

116109
// W channel Handler
117110
let (tok, w_payload, w_valid) = recv_non_blocking(tok, w_ch, zero!<axi_w_t>());
118-
let w_data = if( w_valid ) {
119-
w_payload.wdata
120-
} else {
121-
state.wdata
122-
};
111+
let w_data = if w_valid { w_payload.wdata } else { state.wdata };
123112

124113
// Handle write to CSR
125114
let tok = send_if(tok, write_req, w_valid, csr::WriteWordReq(w_addr, w_data));
126-
let (tok, _, csr_write_valid) = recv_non_blocking(tok, write_resp, csr::WriteResp{});
115+
let (tok, _, csr_write_valid) = recv_non_blocking(tok, write_resp, csr::WriteResp {});
127116

128117
// B Channel Handlers
129118
let b_msg = axi_b_t { bresp: axi_pkg::AXI_WRITE_RESPONSE_CODES::OKAY, bid: uN[ID_W]:0 };
@@ -132,78 +121,59 @@ proc axi_csr<ID_W: u32, ADDR_W: u32, DATA_W: u32, STRB_W: u32, REGS_N: u32> {
132121
// AR Channel Handler
133122
// TODO: #984, zero! does not work
134123
let zero_axi_ar_t = axi_ar_t {
135-
arid : uN[ID_W]:0,
136-
araddr : uN[ADDR_W]:0,
137-
arregion : uN[4]:0,
138-
arlen : uN[8]:0,
139-
arsize : axi_pkg::AXI_AXSIZE_ENCODING::MAX_1B_TRANSFER,
140-
arburst : axi_pkg::AXI_AXBURST_ENCODING::FIXED,
141-
arcache : axi_pkg::AXI_ARCACHE_ENCODING::DEV_NO_BUF,
142-
arprot : uN[3]:0,
143-
arqos : uN[4]:0,
144-
};
145-
let (tok, ar_payload, ar_valid) = recv_non_blocking(tok, ar_ch, zero_axi_ar_t);
146-
let r_addr = if( ar_valid ) {
147-
ar_payload.araddr
148-
} else {
149-
state.raddr
124+
arid: uN[ID_W]:0,
125+
araddr: uN[ADDR_W]:0,
126+
arregion: uN[4]:0,
127+
arlen: uN[8]:0,
128+
arsize: axi_pkg::AXI_AXSIZE_ENCODING::MAX_1B_TRANSFER,
129+
arburst: axi_pkg::AXI_AXBURST_ENCODING::FIXED,
130+
arcache: axi_pkg::AXI_ARCACHE_ENCODING::DEV_NO_BUF,
131+
arprot: uN[3]:0,
132+
arqos: uN[4]:0
150133
};
134+
let (tok, ar_payload, ar_valid) = recv_non_blocking(tok, ar_ch, zero_axi_ar_t);
135+
let r_addr = if ar_valid { ar_payload.araddr } else { state.raddr };
151136

152137
// Handle Read from CSR
153138
let tok = send_if(tok, read_req, ar_valid, csr::ReadWordReq(r_addr));
154-
let (tok, r_data, csr_read_valid) = recv_non_blocking(tok, read_resp, zero!<csr::ReadResp>());
139+
let (tok, r_data, csr_read_valid) =
140+
recv_non_blocking(tok, read_resp, zero!<csr::ReadResp>());
155141

156142
// R Channel Handler
157-
let tok = send_if(tok, r_ch, csr_read_valid, axi_r_t{
158-
rid: uN[ID_W]: 0,
159-
rdata: r_data.data,
160-
rresp: axi_pkg::AXI_READ_RESPONSE_CODES::OKAY,
161-
rlast: uN[1]:1
162-
});
163-
164-
axi_csr_state {
165-
waddr: w_addr,
166-
wdata: w_data,
167-
raddr: r_addr,
168-
rdata: r_data.data
169-
}
143+
let tok = send_if(
144+
tok, r_ch, csr_read_valid,
145+
axi_r_t {
146+
rid: uN[ID_W]:0,
147+
rdata: r_data.data,
148+
rresp: axi_pkg::AXI_READ_RESPONSE_CODES::OKAY,
149+
rlast: uN[1]:1
150+
});
151+
152+
axi_csr_state { waddr: w_addr, wdata: w_data, raddr: r_addr, rdata: r_data.data }
170153
}
171154
}
172155

173156
// Helper functions
174-
pub fn prep_axi_w <ADDR_W:u32,DATA_W:u32, ID_W: u32, STRB_W: u32>(
175-
addr: uN[ADDR_W],
176-
data: uN[DATA_W],
177-
id: uN[ID_W],
178-
strb: uN[STRB_W]) -> (axi_aw_t,axi_w_t){
157+
pub fn prep_axi_w<ADDR_W: u32, DATA_W: u32, ID_W: u32, STRB_W: u32>
158+
(addr: uN[ADDR_W], data: uN[DATA_W], id: uN[ID_W], strb: uN[STRB_W]) -> (axi_aw_t, axi_w_t) {
179159
let aw = axi_aw_t {
180-
awid: id,
181-
awaddr: addr,
182-
awsize: axi_pkg::AXI_AXSIZE_ENCODING::MAX_8B_TRANSFER,
183-
awprot: u3:0
184-
};
185-
let w = axi_w_t {
186-
wdata: data,
187-
wstrb: strb,
188-
wlast: u1:1
160+
awid: id, awaddr: addr, awsize: axi_pkg::AXI_AXSIZE_ENCODING::MAX_8B_TRANSFER, awprot: u3:0
189161
};
162+
let w = axi_w_t { wdata: data, wstrb: strb, wlast: u1:1 };
190163
(aw, w)
191164
}
192165

193-
pub fn prep_axi_r <ADDR_W:u32,ID_W: u32>(
194-
addr: uN[ADDR_W],
195-
id: uN[ID_W],
196-
) -> axi_ar_t {
166+
pub fn prep_axi_r<ADDR_W: u32, ID_W: u32>(addr: uN[ADDR_W], id: uN[ID_W]) -> axi_ar_t {
197167
let ar = axi_ar_t {
198-
arid: id,
199-
araddr: addr,
200-
arregion: uN[4]:0,
201-
arlen: uN[8]:1,
202-
arsize: axi_pkg::AXI_AXSIZE_ENCODING::MAX_1B_TRANSFER,
203-
arburst: axi_pkg::AXI_AXBURST_ENCODING::FIXED,
204-
arcache: axi_pkg::AXI_ARCACHE_ENCODING::DEV_NO_BUF,
205-
arprot: uN[3]:0,
206-
arqos: uN[4]:0
168+
arid: id,
169+
araddr: addr,
170+
arregion: uN[4]:0,
171+
arlen: uN[8]:1,
172+
arsize: axi_pkg::AXI_AXSIZE_ENCODING::MAX_1B_TRANSFER,
173+
arburst: axi_pkg::AXI_AXBURST_ENCODING::FIXED,
174+
arcache: axi_pkg::AXI_ARCACHE_ENCODING::DEV_NO_BUF,
175+
arprot: uN[3]:0,
176+
arqos: uN[4]:0
207177
};
208178

209179
(ar)
@@ -223,8 +193,7 @@ proc test_axi_csr {
223193
b_ch: chan<axi_b_t<TEST_0_ID_W>> in;
224194
ar_ch: chan<axi_ar_t<TEST_0_ID_W, TEST_0_ADDR_W>> out;
225195
r_ch: chan<axi_r_t<TEST_0_ID_W, TEST_0_DATA_W>> in;
226-
227-
all_csr: chan<csr::AllCSR<TEST_0_DATA_W,TEST_0_REGS_N>> in;
196+
all_csr: chan<csr::AllCSR<TEST_0_DATA_W, TEST_0_REGS_N>> in;
228197
terminator: chan<bool> out;
229198

230199
config(terminator: chan<bool> out) {
@@ -233,15 +202,16 @@ proc test_axi_csr {
233202
let (b_req_s, b_req_r) = chan<axi_b_t<TEST_0_ID_W>>;
234203
let (ar_ch_s, ar_ch_r) = chan<axi_ar_t<TEST_0_ID_W, TEST_0_ADDR_W>>;
235204
let (r_ch_s, r_ch_r) = chan<axi_r_t<TEST_0_ID_W, TEST_0_DATA_W>>;
236-
let (all_csr_s, all_csr_r) = chan<csr::AllCSR<TEST_0_DATA_W,TEST_0_REGS_N>>;
205+
let (all_csr_s, all_csr_r) = chan<csr::AllCSR<TEST_0_DATA_W, TEST_0_REGS_N>>;
237206

238207
spawn axi_csr<TEST_0_ID_W, TEST_0_ADDR_W, TEST_0_DATA_W, TEST_0_STRB_W, TEST_0_REGS_N>(
239-
aw_req_r, w_req_r, b_req_s, ar_ch_r, r_ch_s, all_csr_s);
208+
aw_req_r, w_req_r, b_req_s, ar_ch_r, r_ch_s, all_csr_s);
240209
(aw_req_s, w_req_s, b_req_r, ar_ch_s, r_ch_r, all_csr_r, terminator)
241210
}
242211

243212
init { () }
244-
next(tok: token, state:()) {
213+
214+
next(tok: token, state: ()) {
245215
let id = uN[TEST_0_ID_W]:0;
246216
let strb = std::unsigned_max_value<TEST_0_STRB_W>();
247217

@@ -263,7 +233,7 @@ proc test_axi_csr {
263233
let ar = prep_axi_r(addr, id);
264234
let tok = send(tok, ar_ch, ar);
265235
let (tok, rcv) = recv(tok, r_ch);
266-
assert_eq(rcv.rdata,(u32:0xFFFFFFFF + i) as uN[TEST_0_DATA_W] );
236+
assert_eq(rcv.rdata, (u32:0xFFFFFFFF + i) as uN[TEST_0_DATA_W]);
267237
(tok)
268238
}(tok);
269239

@@ -279,17 +249,19 @@ const SYNTH_0_REGS_N = u32:14;
279249

280250
// Verilog example
281251
proc axi_csr_8_32_14 {
282-
config(
283-
aw_ch: chan<axi_aw_t<SYNTH_0_ID_W, SYNTH_0_ADDR_W>> in,
284-
w_ch: chan<axi_w_t<SYNTH_0_DATA_W, SYNTH_0_STRB_W>> in,
285-
b_ch: chan<axi_b_t<SYNTH_0_ID_W>> out,
286-
ar_ch: chan<axi_ar_t<SYNTH_0_ID_W, SYNTH_0_ADDR_W >> in,
287-
r_ch: chan<axi_r_t<SYNTH_0_ID_W, SYNTH_0_DATA_W>> out,
288-
all_csr: chan<csr::AllCSR<SYNTH_0_DATA_W,SYNTH_0_REGS_N>> out
289-
) {spawn axi_csr<SYNTH_0_ID_W, SYNTH_0_ADDR_W, SYNTH_0_DATA_W, SYNTH_0_STRB_W, SYNTH_0_REGS_N>(aw_ch,w_ch,b_ch,ar_ch,
290-
r_ch,all_csr);
291-
()}
252+
config(aw_ch: chan<axi_aw_t<SYNTH_0_ID_W, SYNTH_0_ADDR_W>> in, w_ch
253+
:
254+
chan<axi_w_t<SYNTH_0_DATA_W, SYNTH_0_STRB_W>> in,
255+
b_ch: chan<axi_b_t<SYNTH_0_ID_W>> out, ar_ch: chan<axi_ar_t<SYNTH_0_ID_W, SYNTH_0_ADDR_W>> in, r_ch
256+
:
257+
chan<axi_r_t<SYNTH_0_ID_W, SYNTH_0_DATA_W>> out,
258+
all_csr: chan<csr::AllCSR<SYNTH_0_DATA_W, SYNTH_0_REGS_N>> out) {
259+
spawn axi_csr<SYNTH_0_ID_W, SYNTH_0_ADDR_W, SYNTH_0_DATA_W, SYNTH_0_STRB_W, SYNTH_0_REGS_N>(
260+
aw_ch, w_ch, b_ch, ar_ch, r_ch, all_csr);
261+
()
262+
}
292263

293264
init { () }
294-
next(tok: token, state: ()) {}
265+
266+
next(tok: token, state: ()) { }
295267
}

‎xls/modules/axi4/dma/config.x

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -35,7 +35,7 @@ fn test_axi_config() {
3535
// CSR Config
3636
pub const CSR_DATA_W = AXI_0_DATA_W;
3737
pub const CSR_ADDR_W = AXI_0_ADDR_W;
38-
pub const CSR_REGS_N = u32:14; //std::upow(u32:2, CSR_ADDR_W);
38+
pub const CSR_REGS_N = u32:14; //std::upow(u32:2, CSR_ADDR_W);
3939

4040
// Register Map
4141
pub const CONTROL_REGISTER = uN[CSR_ADDR_W]:0x00;

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