Standardize BUILD names

Signed-off-by: Michal Czyz <[email protected]>

Author: mczyz-antmicro

xls/modules/axi4/dma/BUILD

@@ -72,16 +72,16 @@ xls_ir_opt_ir(
 )
 
 xls_ir_verilog(
-    name = "verilog_csr_8_32_14",
+    name = "verilog_csr",
     src = ":opt_ir_csr_8_32_14.opt.ir",
     codegen_args = {
-        "module_name": "csr_8_32_14",
+        "module_name": "csr",
         "delay_model": "unit",
         "pipeline_stages": "2",
         "reset": "rst",
         "use_system_verilog": "false",
     },
-    verilog_file = "csr_8_32_14.v",
+    verilog_file = "csr.v",
 )
 
 # AXI CSR
@@ -115,7 +115,7 @@ xls_ir_opt_ir(
 )
 
 xls_ir_verilog(
-    name = "axi_csr_verilog",
+    name = "verilog_axi_csr",
     src = ":axi_csr_8_32_14_opt_ir.opt.ir",
     codegen_args = {
         "module_name": "axi_csr",
@@ -128,7 +128,6 @@ xls_ir_verilog(
 )
 
 # FIFO
-
 xls_dslx_library(
     name = 'fifo',
     srcs = [
@@ -156,11 +155,11 @@ xls_ir_opt_ir(
     name = "fifo_ir_opt",
     src = "fifo_ir.ir",
     # FIXME: Top level is not correctly generated in verilog
-    top = "__xls_examples_ram__fifo_synth__FIFO__FifoRAM__RamModel2RW_0__4_8_0_0_16_0_next"
+    top = "__fifo__fifo_synth__FIFO__Writer_0__4_8_1_1_16_1_next"
 )
 
 xls_ir_verilog(
-    name = "fifo_verilog",
+    name = "verilog_fifo",
     src = ":fifo_ir_opt.opt.ir",
     codegen_args = {
         "module_name": "fifo",
@@ -176,38 +175,3 @@ xls_ir_verilog(
     },
     verilog_file = "fifo.v",
 )
-
-# LibA
-xls_dslx_library(
-    name = 'libA',
-    srcs = [
-        'libA.x'
-    ]
-)
-
-xls_dslx_library(
-    name = 'libB',
-    srcs = [
-        'libB.x'
-    ],
-    deps = [
-        'libA'
-    ]
-)
-
-xls_dslx_ir(
-    name = "libB_ir",
-    dslx_top = "procWrapperA",
-    ir_file = "procWrapperA.ir",
-    library = "libB",
-)
-
-xls_dslx_test(
-    name = "test_libA",
-    library = "libA",
-)
-
-xls_dslx_test(
-    name = "test_libB",
-    library = "libB",
-)