Improve support for logic variables in VAST.
#3237
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Enable `logic` module ports like so:
module foo (
logic a,
logic b,
) ...
Expose this functionality on the C API, and add always_comb support to the C API as well.
|
Ah, I didn't see those. Probably the next step is to change codegen (module_builder.cc) to use logic instead of wire and reg. when use_verilog is true. |
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Enable
logicmodule ports like so:module foo (
logic a,
logic b,
) ...
Expose this functionality on the C API, and add always_comb support to the C API as well.