A backup repo of coursework assignments
Result - 69%
| Coursework | Percentage | Marks |
|---|---|---|
| Project feasibility study | 15 | 68 |
| Technical report + Evaluation | 70 | 68 |
| Logbook | 15 | 74 |
Result - 72%
Design assignment - develop an interactive game on a Nexys 4DDR FPGA board. 10 page report, including code appendicies.
- Through the practical use of the Verilog hardware description language (HDL), consolidate understanding of the theory of combinational and sequential circuits and how these combine in the design of digital computing circuits.
- Devise a testing strategy and design a testbench to evaluate the functional correctness of a circuit using the testing features of the Verilog HDL and a professional standard simulator.
| Design | %Marks |
|---|---|
| User control of a moving object on screen with respect for screen boundaries | 10 |
| A map or multiple objects and interactions between them, e.g. collisions | 10 |
| Info bar | 5 |
| Extra features like using other board inputs/outputs (leds, seven segment display, GPIO, accelerometer) | 10 |
| User of sprites from a memory block | 10 |
| Marks for creative design ideas | 5 |
| Report | |
| Introduction and background discussion on displays/VGA | 5 |
| Design description | 25 |
| Testing description | 5 |
| Code quality | 5 |
| Presentation, accordance to report template and references | 5 |
| Reflection section | 5 |
Result - 74%
- Model signals, filters and processes using computer packages.
- Design signal processing systems.
- Apply signal processing systems to classify signals and extract information.
- Evaluate signals and systems using laboratory test and measurement equipment.
| Question 1 | Marks | Result |
|---|---|---|
| a | 4 | 4 |
| b | 9 | 7 |
| c | 8 | 8 |
| d | 6 | 4 |
| e | 12 | 6 |
| Question 2 | ||
| a | 8 | 6 |
| b | 5 | 4 |
| c | 8 | 6 |
| Question 3 | ||
| a | 3 | 3 |
| b | 2 | 2 |
| c | 1 | 1 |
| d | 1 | 0 |
| e | 5 | 4 |
| f | 8 | 5 |
| Question 4 | ||
| a | 4 | 4 |
| b | 3 | 3 |
| c | 2 | 2 |
| d | 1 | 1 |
| e | 5 | 5 |
| f | 5 | 0 |
- Coding Style Deduction: 0
- Execution Penalties (including missing/incorrect output file): 0
- Naming Penalties: -1
Result - 84%
Design assignment - design of a 4-bit magnitude comparator. 2500 word/12 page written report.
- Demonstrate basic knowledge on how different circuit families can be used in IC design for trade-offs in speed, power, complexity and robustness.
- Acquire skills in the use of Electronic Design Automation (EDA) Software for IC design such as Cadence.
- Use CMOS technology, design and analysis techniques for implementation of digital IC systems.
| Description | %Marks |
|---|---|
| Design and functionality of basic cells | 30 |
| Use of hierarchical design including use of structured/standard layout style | 10 |
| Design and functionality of complete (top-cell) magnitude comparator including correct post-layout simulation | 20 |
| Efficient use of area | 20 |
| Number of transistors used | 10 |
| Power consumption and propagation delay measurement results | 10 |
Result - 81%
- Design microwave and RF amplifer circuits.
- Develop expertise in Microwave and RF Simulation/Analysis Tools (AWR DE Microwave Office)
| Part | Marks | Result |
|---|---|---|
| 1 | 16 | 16 |
| 2 | 20 | 16 |
| 3 | 20 | 14 |
| 4 | 20 | 16 |
| 5 | 24 | 19 |
| Total | 100 | 81 |