i2c

SystemVerilog code for I2C master/slave on an FPGA.

Usage

1. Take files from src/ and add them to your own project. If you use hdlmake, you can add this repository itself as a remote module.
2. Other helpful modules are also available in this GitHub organization.
3. Consult the usage example in i2c-demo for code that runs a demo over HDMI.
4. Read through the parameters in i2c_master.sv/i2c_slave.sv and tailor any instantiations to your situation.
5. Please create an issue if you run into a problem or have any questions.

To-do List

• Master
  • SCL
    • Clock stretching
    • Clock synchronization (multi-master)
      • Handle early counter reset
    • Stuck LOW line detection (bus clear via HW reset or Power-On Reset)
    • Release line when bus is free / in use by another master
    • Conformity to stop/repeated start setup & hold times
  • SDA
    • Transmit
    • Receive
    • Arbitration (multi-master) (untested)
      • Basic Implementation
      • Detect other masters triggering start before this master
    • Hotloading (not from i2c spec)
      • Self
        • compensating for jitter of wires connecting/disconnecting... (Schmitt enough?)
        • listen for WAIT_TIME_END to see if the clock is driven LOW
        • if no: bus is free
        • if yes: keep listening until a STOP or START
      • Other masters (untested)
        • erroneous starts detected w/ start_err
  • Port map
• Slave
  • SCL
  • SDA
• Speeds
  • Standard-mode
  • Fast-mode
  • Fast-mode Plus
  • High-speed mode
  • Ultra Fast-mode
• MIPI I3C

Reference Documents

These documents are not hosted here! They are available on Library Genesis and at other locations.

• I2C Specification
• Understanding the I2C Bus
• MIPI I3C Specification