64-bit ARM CPU with 5-stages Pipelining

supported instructions set:

datapath and pipeline logics

(source: https://www.cise.ufl.edu/~mssz/CompOrg/CDA-pipe.html)

Name		Name	Last commit message	Last commit date
Latest commit History 9 Commits
ARM CPU TEST		ARM CPU TEST
benchmarks		benchmarks
db		db
work		work
CPU.sv		CPU.sv
CPU.sv.bak		CPU.sv.bak
DE1_SoC.qpf		DE1_SoC.qpf
DE1_SoC.qsf		DE1_SoC.qsf
DE1_SoC.qws		DE1_SoC.qws
DE1_SoC.sdc		DE1_SoC.sdc
DE1_SoC.srf		DE1_SoC.srf
Launch_ModelSim.bat		Launch_ModelSim.bat
ProgramTheDE1_SoC.cdf		ProgramTheDE1_SoC.cdf
README.md		README.md
bit_ALU.sv		bit_ALU.sv
bit_ALU.sv.bak		bit_ALU.sv.bak
control.sv		control.sv
control.sv.bak		control.sv.bak
datamem.sv		datamem.sv
datapath.sv		datapath.sv
datapath.sv.bak		datapath.sv.bak
decoder2to4.sv		decoder2to4.sv
decoder2to4.sv.bak		decoder2to4.sv.bak
decoder3to8.sv		decoder3to8.sv
decoder3to8.sv.bak		decoder3to8.sv.bak
decoder5to32.sv		decoder5to32.sv
decoder5to32.sv.bak		decoder5to32.sv.bak
dff_64.sv		dff_64.sv
dff_64.sv.bak		dff_64.sv.bak
fa.sv		fa.sv
fa.sv.bak		fa.sv.bak
fetchInstru.sv		fetchInstru.sv
fetchInstru.sv.bak		fetchInstru.sv.bak
forwardingUnit.sv		forwardingUnit.sv
forwardingUnit.sv.bak		forwardingUnit.sv.bak
instructmem.sv		instructmem.sv
instructmem.sv.bak		instructmem.sv.bak
math.sv		math.sv
mux2_1.sv		mux2_1.sv
mux2_1.sv.bak		mux2_1.sv.bak
mux2_1_wave.do		mux2_1_wave.do
mux32_1.sv		mux32_1.sv
mux32_1.sv.bak		mux32_1.sv.bak
mux4_1.sv		mux4_1.sv
mux4_1.sv.bak		mux4_1.sv.bak
regFile.sv		regFile.sv
regFile.sv.bak		regFile.sv.bak
regstim.sv		regstim.sv
runlab.do		runlab.do
signEx.sv		signEx.sv
signEx.sv.bak		signEx.sv.bak
test_flag_33.sv		test_flag_33.sv
test_flag_33.sv.bak		test_flag_33.sv.bak
transcript		transcript
vsim.wlf		vsim.wlf
vsim_stacktrace.vstf		vsim_stacktrace.vstf
wave.do		wave.do
wlft0a6ehc		wlft0a6ehc
wlft8jd3e5		wlft8jd3e5
wlftdtw981		wlftdtw981
wlftf5qm1k		wlftf5qm1k
wlftf9sbzs		wlftf9sbzs
wlftinhqn5		wlftinhqn5
wlftm6izj8		wlftm6izj8

Provide feedback

Saved searches

Use saved searches to filter your results more quickly

Uh oh!

Repository files navigation

64-bit ARM CPU with 5-stages Pipelining

supported instructions set:

datapath and pipeline logics

About

Uh oh!

Releases

Packages

Languages

iaratagram/Virtual-CPU

Folders and files

Latest commit

History

Repository files navigation

64-bit ARM CPU with 5-stages Pipelining

supported instructions set:

datapath and pipeline logics

About

Resources

Uh oh!

Stars

Watchers

Forks

Releases

Packages 0

Languages

Packages