Skip to content

[SYCL][Clang] Add ARM64_SPIRV64 and ARM64SPIR64 target info #18859

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom
Open
wants to merge 4 commits into
base: sycl
Choose a base branch
from
Open

[SYCL][Clang] Add ARM64_SPIRV64 and ARM64SPIR64 target info #18859

wants to merge 4 commits into from

Conversation

hdelan
Copy link
Contributor

@hdelan hdelan commented Jun 9, 2025 •
edited
Loading

Add TargetInfo for MSVC ARM64 host with SPIR64 or SPIRV64 device target.

@hdelan hdelan requested a review from a team as a code owner June 9, 2025 09:37
@hdelan hdelan changed the title Add ARM64_SPIRV64 and ARM64SPIR64 target info [SYCL][Clang] Add ARM64_SPIRV64 and ARM64SPIR64 target info Jun 9, 2025
@hdelan hdelan force-pushed the arm64-clang-info branch from 09dd1ab to 8ca8824 Compare June 9, 2025 09:46
@hdelan
Copy link
Contributor Author

hdelan commented Jun 9, 2025

Hello frens @intel/llvm-reviewers-cuda

@hdelan hdelan force-pushed the arm64-clang-info branch from 8ca8824 to 83bf4de Compare June 9, 2025 10:15
@hdelan hdelan force-pushed the arm64-clang-info branch from 83bf4de to 41e1f96 Compare June 9, 2025 10:16
@hdelan hdelan temporarily deployed to WindowsCILock June 9, 2025 10:16 — with GitHub Actions Inactive
@hdelan hdelan temporarily deployed to WindowsCILock June 9, 2025 10:43 — with GitHub Actions Inactive
@hdelan hdelan temporarily deployed to WindowsCILock June 9, 2025 10:43 — with GitHub Actions Inactive
ldrumm
ldrumm reviewed Jun 9, 2025
View reviewed changes
Report fatal error instead of assert
c822b05 
Instead of asserting false, report a fatal error if the user
provided triple is MSVC and not ARM64 or x64_64 when using
SPIR64 or SPIRV64 device.
@hdelan hdelan temporarily deployed to WindowsCILock June 9, 2025 14:28 — with GitHub Actions Inactive
@hdelan hdelan temporarily deployed to WindowsCILock June 9, 2025 15:25 — with GitHub Actions Inactive
@hdelan hdelan temporarily deployed to WindowsCILock June 9, 2025 15:25 — with GitHub Actions Inactive
steffenlarsen
steffenlarsen reviewed Jun 10, 2025
View reviewed changes
@hdelan hdelan temporarily deployed to WindowsCILock June 10, 2025 07:27 — with GitHub Actions Inactive
steffenlarsen
steffenlarsen approved these changes Jun 10, 2025
View reviewed changes
Copy link
Contributor

@steffenlarsen steffenlarsen left a comment

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

I think it looks good, but I wonder if this could benefit upstream LLVM as well. Seems like at least some of it is independent of SYCL.

@hdelan hdelan temporarily deployed to WindowsCILock June 10, 2025 07:58 — with GitHub Actions Inactive
@Naghasan
Copy link
Contributor

I think it looks good, but I wonder if this could benefit upstream LLVM as well. Seems like at least some of it is independent of SYCL.

I'm not 100% sure there is the basic infrastructure yet for this. But I think it would be nice to stop creating these hardcoded subvariants (it'll probably not fly well upstream anyway), they are hacks and it doesn't scale. E.g. AMD has one TargetInfo and NV has 2 (for the 32 and 64 variants) and that enough to support all host...

We only need the SPIRTargetInfo, SPIR64TargetInfo, SPIRV32TargetInfo and SPIRV64TargetInfo variants and a proper implementation of setAuxTarget to copy the info from the host triple. NOTE: SPIRVTargetInfo is for the Shader variant, so not required for SYCL.

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Reviewers

@ldrumm ldrumm ldrumm left review comments

@steffenlarsen steffenlarsen steffenlarsen approved these changes

At least 1 approving review is required to merge this pull request.

Assignees
No one assigned
Labels
None yet
Projects
None yet
Milestone
No milestone
Development

Successfully merging this pull request may close these issues.
4 participants
@hdelan @Naghasan @ldrumm @steffenlarsen