Quartus Flow

Quartus Flow

• Copy $HLD_ROOT/rtl/5.0.3/par/bdw_hld_top.qsf.sample to your Quartus directory and rename it to bdw_hld_top.qsf
• Edit bdw_hld_top.qsf to set necessary variables (HLS_V_LIST takes .f file generated by CtoS using "write_rtl -verilog_module per_sc_module" command). You may also need to append bdw_hld_top.qsf with MPF configuration from your BBB package:

set CCI_MPF_SRC "PATH_TO_BBBs/BBB_cci_mpf"
set_global_assignment -name VERILOG_MACRO "MPF_PLATFORM_BDX=1"
source $CCI_MPF_SRC/hw/par/qsf_cci_mpf_PAR_files.qsf

• Create a symbolic link in the Quartus directory

ln -s $HLD_ROOT/rtl/5.0.3/par/hld_shim.sdc .

• In the end of bdw_503_pr_afu_synth.qsf, add this line:

source bdw_hld_top.qsf

• In the end of bdw_503_pr_afu.qsf, add this line:

set_global_assignment -name SDC_FILE hld_shim.sdc