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Add riscv64 binding #28
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This commit add perf-even-open-sys riscv64 binding. Binding is generated from Arch Linux RISC-V with kernel headers 6.0.9 on SiFive Unmatched RISC-V board. Build verfied on SiFive Unmatched RISC-V board. Signed-off-by: Avimitin <[email protected]>
I am wondering when this PR can be merged. I tested this PR because I happened to measuredd some IPC numbers on SiFive Unmatched board, and it reports same result as using perf. |
I tried this PR on a VisionFive2 board from StarFive, and could not get any of the examples to work. I built a project with the println.rs example and got this when running: This happens on line: I'm new to this so I would need help with pointers on where to look how to debug this. I'm on: |
@matsbror My experience with |
I'm not sure I understand what you mean by "also include OS when running perf". Can you elaborate? It's unfortunate that I cannot use group, but the example I was running did not use Group. |
Yes. In my case, I need to call let mut total_inst = Builder::new()
.include_kernel()
.include_hv()
.kind(events::Hardware::INSTRUCTIONS)
.any_pid()
.one_cpu(1)
.build()
.unwrap(); These functions are not available for the crate in crates.rs, but is available in current repository. |
Thanks, this was indeed helpful. I tried using Group and all counters returned 0. Do you have any idea why groups cannot be used? |
I have no idea. Maybe the board does not have hardware support to read multiple counters atomically. |
By trial and error I found that Groups does wok for my board. I just need to be careful which counters I am using. It works apparently only for the ones supported in hardware. |
This PR add perf-even-open-sys riscv64 binding. Binding is generated from Arch Linux RISC-V with kernel headers 6.0.9 on SiFive Unmatched RISC-V board. Build verfied on SiFive Unmatched RISC-V board.
Signed-off-by: Avimitin [email protected]