🔴 SystemVerilog FPGA cores to communicate with FTDI Synchronous/Asynchronous FIFOs (FT245 protocol)

Fast parser for Saleae Logic 2 binary export format (Digital only, Linux only)

2D vector & raster editor that melds traditional layers & tools with a modern node-based, non-destructive, procedural workflow.

Python interface to Optotune focus-tunable lenses

SystemVerilog UVM testbench example

The High-Frequency Trading FPGA System is an ultra-low latency platform for electronic trading on FPGAs. It features a TCP/IP stack, order matching engine, custom IP core, and risk management modul…

I will be implementing the LC-3 ISA specifications in verilog.

A collection of hardware and software projects based around the Electro-Smith Daisy Seed

Ravi is a dialect of Lua, featuring limited optional static typing, JIT and AOT compilers

Statically Allocated Embedded C container LIBrary

Euclidean drum machine maybe one day suitable for deploying onto ipad running pdparty

NAND flash translation layer for low-memory systems

book for parents and kids.

Sample code for the PedalPCB Terrarium.

A reverb example for the terrarium from PedalPCB

An open source cross-platform USB stack for embedded system

Opensource, Skywater PDK, Digital design, OPENLANE, Analog design

BaseJump STL: A Standard Template Library for SystemVerilog

3D-printable hexagonal mirror array capable of reflecting sunlight into arbitrary patterns

Verilog Ethernet components for FPGA implementation

John's Field-Programmable JPEG Compressor; a jpeg compressor written in verilog. Currently targeted to deploy to Lattice's iCE40 up5k fpga.

lowRISC Style Guides

experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.

Eurorack modules

STM32F project template and utility routines used for Mutable Instruments products