This repository contains lab projects for COMPE 470L, a digital design course focused on FPGA development using the Basys 3 board and Verilog. The labs cover key topics such as state machines, LED control, counters, and UART communication.
- FPGA Board: Basys 3 (Xilinx Artix-7)
- Language: Verilog
- Software: Vivado
The repository is structured with separate folders for each lab. Topics include:
- 🔹 LED Control & Counters – Implementing basic logic and sequential circuits
- 🔹 State Machines – Designing and testing finite state machines
- 🔹 UART Communication – Serial communication with external devices
- 🔹 More to Come – Additional labs will be added as the course progresses
This repository is actively being developed as I progress through the course. Future updates will include additional labs, optimizations, and insights gained along the way.
- Getting familiar with the Vivado environment and FPGA toolchain
- Debugging Verilog designs and understanding synthesis vs. simulation
- Implementing efficient state machines and hardware design principles
This repository serves as a learning resource, and the code may evolve over time as I refine my understanding of FPGA design and hardware description languages.