Skip to content

[AArch64] Change IssueWidth to 5 in AArch64SchedNeoverseN2.td #145717

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 1 commit into from
Jun 30, 2025
+2,023 −2,019
Merged

[AArch64] Change IssueWidth to 5 in AArch64SchedNeoverseN2.td #145717

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
2 changes: 1 addition & 1 deletion llvm/lib/Target/AArch64/AArch64SchedNeoverseN2.td
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -11,7 +11,7 @@
//===----------------------------------------------------------------------===//

def NeoverseN2Model : SchedMachineModel {
let IssueWidth = 10; // Micro-ops dispatched at a time.
let IssueWidth = 5; // Micro-ops dispatched at a time.
let MicroOpBufferSize = 160; // Entries in micro-op re-order buffer.
let LoadLatency = 4; // Optimistic load latency.
let MispredictPenalty = 10; // Extra cycles for mispredicted branch.
Expand Down
8 changes: 4 additions & 4 deletions llvm/test/CodeGen/AArch64/machine-combiner.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -262,8 +262,8 @@ define half @reassociate_adds_half(half %x0, half %x1, half %x2, half %x3) {
; CHECK-UNSAFE-LABEL: reassociate_adds_half:
; CHECK-UNSAFE: // %bb.0:
; CHECK-UNSAFE-NEXT: fdiv h0, h0, h1
; CHECK-UNSAFE-NEXT: fadd h2, h3, h2
; CHECK-UNSAFE-NEXT: fadd h0, h2, h0
; CHECK-UNSAFE-NEXT: fadd h1, h3, h2
; CHECK-UNSAFE-NEXT: fadd h0, h1, h0
; CHECK-UNSAFE-NEXT: ret
%t0 = fdiv half %x0, %x1
%t1 = fadd half %x2, %t0
Expand All @@ -284,8 +284,8 @@ define half @reassociate_muls_half(half %x0, half %x1, half %x2, half %x3) {
; CHECK-UNSAFE-LABEL: reassociate_muls_half:
; CHECK-UNSAFE: // %bb.0:
; CHECK-UNSAFE-NEXT: fdiv h0, h0, h1
; CHECK-UNSAFE-NEXT: fmul h2, h3, h2
; CHECK-UNSAFE-NEXT: fmul h0, h2, h0
; CHECK-UNSAFE-NEXT: fmul h1, h3, h2
; CHECK-UNSAFE-NEXT: fmul h0, h1, h0
; CHECK-UNSAFE-NEXT: ret
%t0 = fdiv half %x0, %x1
%t1 = fmul half %x2, %t0
Expand Down
18 changes: 9 additions & 9 deletions llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-sve-instructions.s
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -5066,19 +5066,19 @@ zip2 z31.s, z31.s, z31.s
# CHECK-NEXT: 2 2 1.00 movs p0.b, p0/z, p0.b
# CHECK-NEXT: 2 2 1.00 movs p15.b, p15.b
# CHECK-NEXT: 2 2 1.00 movs p15.b, p15/z, p15.b
# CHECK-NEXT: 1 1 0.10 U mrs x3, ID_AA64ZFR0_EL1
# CHECK-NEXT: 1 1 0.10 U mrs x3, ZCR_EL1
# CHECK-NEXT: 1 1 0.10 U mrs x3, ZCR_EL12
# CHECK-NEXT: 1 1 0.10 U mrs x3, ZCR_EL2
# CHECK-NEXT: 1 1 0.10 U mrs x3, ZCR_EL3
# CHECK-NEXT: 1 1 0.20 U mrs x3, ID_AA64ZFR0_EL1
# CHECK-NEXT: 1 1 0.20 U mrs x3, ZCR_EL1
# CHECK-NEXT: 1 1 0.20 U mrs x3, ZCR_EL12
# CHECK-NEXT: 1 1 0.20 U mrs x3, ZCR_EL2
# CHECK-NEXT: 1 1 0.20 U mrs x3, ZCR_EL3
# CHECK-NEXT: 1 4 1.00 msb z0.b, p7/m, z1.b, z31.b
# CHECK-NEXT: 2 5 2.00 msb z0.d, p7/m, z1.d, z31.d
# CHECK-NEXT: 1 4 1.00 msb z0.h, p7/m, z1.h, z31.h
# CHECK-NEXT: 1 4 1.00 msb z0.s, p7/m, z1.s, z31.s
# CHECK-NEXT: 1 1 0.10 U msr ZCR_EL1, x3
# CHECK-NEXT: 1 1 0.10 U msr ZCR_EL12, x3
# CHECK-NEXT: 1 1 0.10 U msr ZCR_EL2, x3
# CHECK-NEXT: 1 1 0.10 U msr ZCR_EL3, x3
# CHECK-NEXT: 1 1 0.20 U msr ZCR_EL1, x3
# CHECK-NEXT: 1 1 0.20 U msr ZCR_EL12, x3
# CHECK-NEXT: 1 1 0.20 U msr ZCR_EL2, x3
# CHECK-NEXT: 1 1 0.20 U msr ZCR_EL3, x3
# CHECK-NEXT: 1 4 1.00 mul z0.b, p7/m, z0.b, z31.b
# CHECK-NEXT: 1 4 1.00 mul z0.b, z1.b, z2.b
# CHECK-NEXT: 2 5 2.00 mul z0.d, p7/m, z0.d, z31.d
Expand Down
Loading
Loading