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Precommit test for PR #171012 #171013

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@gandhi56 gandhi56 commented Dec 7, 2025

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@gandhi56 gandhi56 self-assigned this Dec 7, 2025
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llvmbot commented Dec 7, 2025

@llvm/pr-subscribers-backend-amdgpu

Author: Anshil Gandhi (gandhi56)

Changes

Patch is 93.13 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/171013.diff

1 Files Affected:

  • (added) llvm/test/CodeGen/AMDGPU/local-stack-alloc-sort-framerefs.mir (+1093)
diff --git a/llvm/test/CodeGen/AMDGPU/local-stack-alloc-sort-framerefs.mir b/llvm/test/CodeGen/AMDGPU/local-stack-alloc-sort-framerefs.mir
new file mode 100644
index 0000000000000..d3eac690312bc
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/local-stack-alloc-sort-framerefs.mir
@@ -0,0 +1,1093 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx950 -run-pass=localstackalloc -verify-machineinstrs -o - %s | FileCheck %s
+
+---
+name:            issue155902
+alignment:       1
+exposesReturnsTwice: false
+legalized:       false
+regBankSelected: false
+selected:        false
+failedISel:      false
+tracksRegLiveness: true
+hasWinCFI:       false
+noPhis:          false
+isSSA:           true
+noVRegs:         false
+hasFakeUses:     false
+callsEHReturn:   false
+callsUnwindInit: false
+hasEHContTarget: false
+hasEHScopes:     false
+hasEHFunclets:   false
+isOutlined:      false
+debugInstrRef:   false
+failsVerification: false
+tracksDebugUserValues: false
+registers:
+  - { id: 0, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 1, class: sgpr_64, preferred-register: '', flags: [  ] }
+  - { id: 2, class: sgpr_64, preferred-register: '', flags: [  ] }
+  - { id: 3, class: sgpr_64, preferred-register: '', flags: [  ] }
+  - { id: 4, class: sgpr_64, preferred-register: '', flags: [  ] }
+  - { id: 5, class: sgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 6, class: sgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 7, class: sgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 8, class: sreg_64_xexec, preferred-register: '', flags: [  ] }
+  - { id: 9, class: sreg_64_xexec, preferred-register: '', flags: [  ] }
+  - { id: 10, class: sreg_64_xexec, preferred-register: '', flags: [  ] }
+  - { id: 11, class: sreg_64_xexec, preferred-register: '', flags: [  ] }
+  - { id: 12, class: sreg_64_xexec, preferred-register: '', flags: [  ] }
+  - { id: 13, class: sreg_64_xexec, preferred-register: '', flags: [  ] }
+  - { id: 14, class: sreg_64_xexec, preferred-register: '', flags: [  ] }
+  - { id: 15, class: sreg_64_xexec, preferred-register: '', flags: [  ] }
+  - { id: 16, class: sreg_64_xexec, preferred-register: '', flags: [  ] }
+  - { id: 17, class: sreg_64_xexec, preferred-register: '', flags: [  ] }
+  - { id: 18, class: sreg_64_xexec, preferred-register: '', flags: [  ] }
+  - { id: 19, class: sreg_64_xexec, preferred-register: '', flags: [  ] }
+  - { id: 20, class: sreg_64_xexec, preferred-register: '', flags: [  ] }
+  - { id: 21, class: sreg_64_xexec, preferred-register: '', flags: [  ] }
+  - { id: 22, class: sreg_64_xexec, preferred-register: '', flags: [  ] }
+  - { id: 23, class: sreg_64_xexec, preferred-register: '', flags: [  ] }
+  - { id: 24, class: sreg_64_xexec, preferred-register: '', flags: [  ] }
+  - { id: 25, class: sreg_64_xexec, preferred-register: '', flags: [  ] }
+  - { id: 26, class: sreg_64_xexec, preferred-register: '', flags: [  ] }
+  - { id: 27, class: sreg_64_xexec, preferred-register: '', flags: [  ] }
+  - { id: 28, class: sreg_64_xexec, preferred-register: '', flags: [  ] }
+  - { id: 29, class: sreg_64_xexec, preferred-register: '', flags: [  ] }
+  - { id: 30, class: sreg_64_xexec, preferred-register: '', flags: [  ] }
+  - { id: 31, class: sreg_64_xexec, preferred-register: '', flags: [  ] }
+  - { id: 32, class: sreg_64_xexec, preferred-register: '', flags: [  ] }
+  - { id: 33, class: sreg_64_xexec, preferred-register: '', flags: [  ] }
+  - { id: 34, class: sreg_64_xexec, preferred-register: '', flags: [  ] }
+  - { id: 35, class: sreg_64_xexec, preferred-register: '', flags: [  ] }
+  - { id: 36, class: sreg_64_xexec, preferred-register: '', flags: [  ] }
+  - { id: 37, class: sreg_64_xexec, preferred-register: '', flags: [  ] }
+  - { id: 38, class: sreg_64_xexec, preferred-register: '', flags: [  ] }
+  - { id: 39, class: sreg_64_xexec, preferred-register: '', flags: [  ] }
+  - { id: 40, class: sreg_64_xexec, preferred-register: '', flags: [  ] }
+  - { id: 41, class: sreg_64_xexec, preferred-register: '', flags: [  ] }
+  - { id: 42, class: sreg_64_xexec, preferred-register: '', flags: [  ] }
+  - { id: 43, class: sreg_64_xexec, preferred-register: '', flags: [  ] }
+  - { id: 44, class: sreg_64_xexec, preferred-register: '', flags: [  ] }
+  - { id: 45, class: sreg_64_xexec, preferred-register: '', flags: [  ] }
+  - { id: 46, class: sreg_64_xexec, preferred-register: '', flags: [  ] }
+  - { id: 47, class: sreg_64_xexec, preferred-register: '', flags: [  ] }
+  - { id: 48, class: sreg_64_xexec, preferred-register: '', flags: [  ] }
+  - { id: 49, class: sreg_64_xexec, preferred-register: '', flags: [  ] }
+  - { id: 50, class: sreg_64_xexec, preferred-register: '', flags: [  ] }
+  - { id: 51, class: sreg_64_xexec, preferred-register: '', flags: [  ] }
+  - { id: 52, class: sreg_64_xexec, preferred-register: '', flags: [  ] }
+  - { id: 53, class: sreg_64_xexec, preferred-register: '', flags: [  ] }
+  - { id: 54, class: sreg_64_xexec, preferred-register: '', flags: [  ] }
+  - { id: 55, class: sreg_64_xexec, preferred-register: '', flags: [  ] }
+  - { id: 56, class: sreg_64_xexec, preferred-register: '', flags: [  ] }
+  - { id: 57, class: sreg_64_xexec, preferred-register: '', flags: [  ] }
+  - { id: 58, class: vreg_64_align2, preferred-register: '', flags: [  ] }
+  - { id: 59, class: vreg_64_align2, preferred-register: '', flags: [  ] }
+  - { id: 60, class: av_64_align2, preferred-register: '', flags: [  ] }
+  - { id: 61, class: av_64_align2, preferred-register: '', flags: [  ] }
+  - { id: 62, class: av_64_align2, preferred-register: '', flags: [  ] }
+  - { id: 63, class: av_64_align2, preferred-register: '', flags: [  ] }
+  - { id: 64, class: av_64_align2, preferred-register: '', flags: [  ] }
+  - { id: 65, class: av_64_align2, preferred-register: '', flags: [  ] }
+  - { id: 66, class: av_64_align2, preferred-register: '', flags: [  ] }
+  - { id: 67, class: av_64_align2, preferred-register: '', flags: [  ] }
+  - { id: 68, class: av_64_align2, preferred-register: '', flags: [  ] }
+  - { id: 69, class: av_64_align2, preferred-register: '', flags: [  ] }
+  - { id: 70, class: av_64_align2, preferred-register: '', flags: [  ] }
+  - { id: 71, class: av_64_align2, preferred-register: '', flags: [  ] }
+  - { id: 72, class: av_64_align2, preferred-register: '', flags: [  ] }
+  - { id: 73, class: av_64_align2, preferred-register: '', flags: [  ] }
+  - { id: 74, class: av_64_align2, preferred-register: '', flags: [  ] }
+  - { id: 75, class: av_64_align2, preferred-register: '', flags: [  ] }
+  - { id: 76, class: av_64_align2, preferred-register: '', flags: [  ] }
+  - { id: 77, class: av_64_align2, preferred-register: '', flags: [  ] }
+  - { id: 78, class: av_64_align2, preferred-register: '', flags: [  ] }
+  - { id: 79, class: av_64_align2, preferred-register: '', flags: [  ] }
+  - { id: 80, class: av_64_align2, preferred-register: '', flags: [  ] }
+  - { id: 81, class: av_64_align2, preferred-register: '', flags: [  ] }
+  - { id: 82, class: av_64_align2, preferred-register: '', flags: [  ] }
+  - { id: 83, class: av_64_align2, preferred-register: '', flags: [  ] }
+  - { id: 84, class: av_64_align2, preferred-register: '', flags: [  ] }
+  - { id: 85, class: av_64_align2, preferred-register: '', flags: [  ] }
+  - { id: 86, class: av_64_align2, preferred-register: '', flags: [  ] }
+  - { id: 87, class: av_64_align2, preferred-register: '', flags: [  ] }
+  - { id: 88, class: av_64_align2, preferred-register: '', flags: [  ] }
+  - { id: 89, class: av_64_align2, preferred-register: '', flags: [  ] }
+  - { id: 90, class: av_64_align2, preferred-register: '', flags: [  ] }
+  - { id: 91, class: av_64_align2, preferred-register: '', flags: [  ] }
+  - { id: 92, class: av_64_align2, preferred-register: '', flags: [  ] }
+  - { id: 93, class: av_64_align2, preferred-register: '', flags: [  ] }
+  - { id: 94, class: av_64_align2, preferred-register: '', flags: [  ] }
+  - { id: 95, class: av_64_align2, preferred-register: '', flags: [  ] }
+  - { id: 96, class: av_64_align2, preferred-register: '', flags: [  ] }
+  - { id: 97, class: av_64_align2, preferred-register: '', flags: [  ] }
+  - { id: 98, class: av_64_align2, preferred-register: '', flags: [  ] }
+  - { id: 99, class: av_64_align2, preferred-register: '', flags: [  ] }
+  - { id: 100, class: av_64_align2, preferred-register: '', flags: [  ] }
+  - { id: 101, class: av_64_align2, preferred-register: '', flags: [  ] }
+  - { id: 102, class: av_64_align2, preferred-register: '', flags: [  ] }
+  - { id: 103, class: av_64_align2, preferred-register: '', flags: [  ] }
+  - { id: 104, class: av_64_align2, preferred-register: '', flags: [  ] }
+  - { id: 105, class: av_64_align2, preferred-register: '', flags: [  ] }
+  - { id: 106, class: av_64_align2, preferred-register: '', flags: [  ] }
+  - { id: 107, class: av_64_align2, preferred-register: '', flags: [  ] }
+  - { id: 108, class: av_64_align2, preferred-register: '', flags: [  ] }
+  - { id: 109, class: av_64_align2, preferred-register: '', flags: [  ] }
+liveins:
+  - { reg: '$sgpr4_sgpr5', virtual-reg: '%3' }
+frameInfo:
+  isFrameAddressTaken: false
+  isReturnAddressTaken: false
+  hasStackMap:     false
+  hasPatchPoint:   false
+  stackSize:       0
+  offsetAdjustment: 0
+  maxAlignment:    8
+  adjustsStack:    false
+  hasCalls:        false
+  stackProtector:  ''
+  functionContext: ''
+  maxCallFrameSize: 4294967295
+  cvBytesOfCalleeSavedRegisters: 0
+  hasOpaqueSPAdjustment: false
+  hasVAStart:      false
+  hasMustTailInVarArgFunc: false
+  hasTailCall:     false
+  isCalleeSavedInfoValid: false
+  localFrameSize:  0
+fixedStack:      []
+stack:
+  - { id: 0, type: default, offset: 0, size: 16384, alignment: 4,
+      stack-id: default, callee-saved-register: '', callee-saved-restored: true,
+      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+  - { id: 1, type: default, offset: 0, size: 16, alignment: 8,
+      stack-id: default, callee-saved-register: '', callee-saved-restored: true,
+      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+  - { id: 2, type: default, offset: 0, size: 8, alignment: 8,
+      stack-id: default, callee-saved-register: '', callee-saved-restored: true,
+      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+entry_values:    []
+callSites:       []
+debugValueSubstitutions: []
+constants:       []
+machineFunctionInfo:
+  explicitKernArgSize: 400
+  maxKernArgAlign: 8
+  ldsSize:         0
+  gdsSize:         0
+  dynLDSAlign:     1
+  isEntryFunction: true
+  isChainFunction: false
+  noSignedZerosFPMath: false
+  memoryBound:     false
+  waveLimiter:     false
+  hasSpilledSGPRs: false
+  hasSpilledVGPRs: false
+  numWaveDispatchSGPRs: 0
+  numWaveDispatchVGPRs: 0
+  scratchRSrcReg:  '$private_rsrc_reg'
+  frameOffsetReg:  '$fp_reg'
+  stackPtrOffsetReg: '$sgpr32'
+  bytesInStackArgArea: 0
+  returnsVoid:     true
+  argumentInfo:
+    dispatchPtr:     { reg: '$sgpr0_sgpr1' }
+    queuePtr:        { reg: '$sgpr2_sgpr3' }
+    kernargSegmentPtr: { reg: '$sgpr4_sgpr5' }
+    dispatchID:      { reg: '$sgpr6_sgpr7' }
+    workGroupIDX:    { reg: '$sgpr8' }
+    workGroupIDY:    { reg: '$sgpr9' }
+    workGroupIDZ:    { reg: '$sgpr10' }
+    workItemIDX:     { reg: '$vgpr0', mask: 1023 }
+    workItemIDY:     { reg: '$vgpr0', mask: 1047552 }
+    workItemIDZ:     { reg: '$vgpr0', mask: 1072693248 }
+  psInputAddr:     0
+  psInputEnable:   0
+  maxMemoryClusterDWords: 8
+  mode:
+    ieee:            true
+    dx10-clamp:      true
+    fp32-input-denormals: true
+    fp32-output-denormals: true
+    fp64-fp16-input-denormals: true
+    fp64-fp16-output-denormals: true
+  highBitsOf32BitAddress: 0
+  occupancy:       8
+  vgprForAGPRCopy: ''
+  sgprForEXECCopy: '$sgpr100_sgpr101'
+  longBranchReservedReg: ''
+  hasInitWholeWave: false
+  dynamicVGPRBlockSize: 0
+  scratchReservedForDynamicVGPRs: 0
+  numKernargPreloadSGPRs: 0
+  isWholeWaveFunction: false
+body:             |
+  bb.0:
+    liveins: $sgpr4_sgpr5
+
+    ; CHECK-LABEL: name: issue155902
+    ; CHECK: liveins: $sgpr4_sgpr5
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xexec_hi = S_MOV_B32 %stack.1
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr_64(p4) = COPY $sgpr4_sgpr5
+    ; CHECK-NEXT: [[S_LOAD_DWORDX2_IMM:%[0-9]+]]:sreg_64_xexec = S_LOAD_DWORDX2_IMM [[COPY]](p4), 0, 0 :: (dereferenceable invariant load (s64), align 16, addrspace 4)
+    ; CHECK-NEXT: [[S_LOAD_DWORDX2_IMM1:%[0-9]+]]:sreg_64_xexec = S_LOAD_DWORDX2_IMM [[COPY]](p4), 8, 0 :: (dereferenceable invariant load (s64), addrspace 4)
+    ; CHECK-NEXT: [[S_LOAD_DWORDX2_IMM2:%[0-9]+]]:sreg_64_xexec = S_LOAD_DWORDX2_IMM [[COPY]](p4), 16, 0 :: (dereferenceable invariant load (s64), align 16, addrspace 4)
+    ; CHECK-NEXT: [[S_LOAD_DWORDX2_IMM3:%[0-9]+]]:sreg_64_xexec = S_LOAD_DWORDX2_IMM [[COPY]](p4), 24, 0 :: (dereferenceable invariant load (s64), addrspace 4)
+    ; CHECK-NEXT: [[S_LOAD_DWORDX2_IMM4:%[0-9]+]]:sreg_64_xexec = S_LOAD_DWORDX2_IMM [[COPY]](p4), 32, 0 :: (dereferenceable invariant load (s64), align 16, addrspace 4)
+    ; CHECK-NEXT: [[S_LOAD_DWORDX2_IMM5:%[0-9]+]]:sreg_64_xexec = S_LOAD_DWORDX2_IMM [[COPY]](p4), 40, 0 :: (dereferenceable invariant load (s64), addrspace 4)
+    ; CHECK-NEXT: [[S_LOAD_DWORDX2_IMM6:%[0-9]+]]:sreg_64_xexec = S_LOAD_DWORDX2_IMM [[COPY]](p4), 48, 0 :: (dereferenceable invariant load (s64), align 16, addrspace 4)
+    ; CHECK-NEXT: [[S_LOAD_DWORDX2_IMM7:%[0-9]+]]:sreg_64_xexec = S_LOAD_DWORDX2_IMM [[COPY]](p4), 56, 0 :: (dereferenceable invariant load (s64), addrspace 4)
+    ; CHECK-NEXT: [[S_LOAD_DWORDX2_IMM8:%[0-9]+]]:sreg_64_xexec = S_LOAD_DWORDX2_IMM [[COPY]](p4), 64, 0 :: (dereferenceable invariant load (s64), align 16, addrspace 4)
+    ; CHECK-NEXT: [[S_LOAD_DWORDX2_IMM9:%[0-9]+]]:sreg_64_xexec = S_LOAD_DWORDX2_IMM [[COPY]](p4), 72, 0 :: (dereferenceable invariant load (s64), addrspace 4)
+    ; CHECK-NEXT: [[S_LOAD_DWORDX2_IMM10:%[0-9]+]]:sreg_64_xexec = S_LOAD_DWORDX2_IMM [[COPY]](p4), 80, 0 :: (dereferenceable invariant load (s64), align 16, addrspace 4)
+    ; CHECK-NEXT: [[S_LOAD_DWORDX2_IMM11:%[0-9]+]]:sreg_64_xexec = S_LOAD_DWORDX2_IMM [[COPY]](p4), 88, 0 :: (dereferenceable invariant load (s64), addrspace 4)
+    ; CHECK-NEXT: [[S_LOAD_DWORDX2_IMM12:%[0-9]+]]:sreg_64_xexec = S_LOAD_DWORDX2_IMM [[COPY]](p4), 96, 0 :: (dereferenceable invariant load (s64), align 16, addrspace 4)
+    ; CHECK-NEXT: [[S_LOAD_DWORDX2_IMM13:%[0-9]+]]:sreg_64_xexec = S_LOAD_DWORDX2_IMM [[COPY]](p4), 104, 0 :: (dereferenceable invariant load (s64), addrspace 4)
+    ; CHECK-NEXT: [[S_LOAD_DWORDX2_IMM14:%[0-9]+]]:sreg_64_xexec = S_LOAD_DWORDX2_IMM [[COPY]](p4), 112, 0 :: (dereferenceable invariant load (s64), align 16, addrspace 4)
+    ; CHECK-NEXT: [[S_LOAD_DWORDX2_IMM15:%[0-9]+]]:sreg_64_xexec = S_LOAD_DWORDX2_IMM [[COPY]](p4), 120, 0 :: (dereferenceable invariant load (s64), addrspace 4)
+    ; CHECK-NEXT: [[S_LOAD_DWORDX2_IMM16:%[0-9]+]]:sreg_64_xexec = S_LOAD_DWORDX2_IMM [[COPY]](p4), 128, 0 :: (dereferenceable invariant load (s64), align 16, addrspace 4)
+    ; CHECK-NEXT: [[S_LOAD_DWORDX2_IMM17:%[0-9]+]]:sreg_64_xexec = S_LOAD_DWORDX2_IMM [[COPY]](p4), 136, 0 :: (dereferenceable invariant load (s64), addrspace 4)
+    ; CHECK-NEXT: [[S_LOAD_DWORDX2_IMM18:%[0-9]+]]:sreg_64_xexec = S_LOAD_DWORDX2_IMM [[COPY]](p4), 144, 0 :: (dereferenceable invariant load (s64), align 16, addrspace 4)
+    ; CHECK-NEXT: [[S_LOAD_DWORDX2_IMM19:%[0-9]+]]:sreg_64_xexec = S_LOAD_DWORDX2_IMM [[COPY]](p4), 152, 0 :: (dereferenceable invariant load (s64), addrspace 4)
+    ; CHECK-NEXT: [[S_LOAD_DWORDX2_IMM20:%[0-9]+]]:sreg_64_xexec = S_LOAD_DWORDX2_IMM [[COPY]](p4), 160, 0 :: (dereferenceable invariant load (s64), align 16, addrspace 4)
+    ; CHECK-NEXT: [[S_LOAD_DWORDX2_IMM21:%[0-9]+]]:sreg_64_xexec = S_LOAD_DWORDX2_IMM [[COPY]](p4), 168, 0 :: (dereferenceable invariant load (s64), addrspace 4)
+    ; CHECK-NEXT: [[S_LOAD_DWORDX2_IMM22:%[0-9]+]]:sreg_64_xexec = S_LOAD_DWORDX2_IMM [[COPY]](p4), 176, 0 :: (dereferenceable invariant load (s64), align 16, addrspace 4)
+    ; CHECK-NEXT: [[S_LOAD_DWORDX2_IMM23:%[0-9]+]]:sreg_64_xexec = S_LOAD_DWORDX2_IMM [[COPY]](p4), 184, 0 :: (dereferenceable invariant load (s64), addrspace 4)
+    ; CHECK-NEXT: [[S_LOAD_DWORDX2_IMM24:%[0-9]+]]:sreg_64_xexec = S_LOAD_DWORDX2_IMM [[COPY]](p4), 192, 0 :: (dereferenceable invariant load (s64), align 16, addrspace 4)
+    ; CHECK-NEXT: [[S_LOAD_DWORDX2_IMM25:%[0-9]+]]:sreg_64_xexec = S_LOAD_DWORDX2_IMM [[COPY]](p4), 200, 0 :: (dereferenceable invariant load (s64), addrspace 4)
+    ; CHECK-NEXT: [[S_LOAD_DWORDX2_IMM26:%[0-9]+]]:sreg_64_xexec = S_LOAD_DWORDX2_IMM [[COPY]](p4), 208, 0 :: (dereferenceable invariant load (s64), align 16, addrspace 4)
+    ; CHECK-NEXT: [[S_LOAD_DWORDX2_IMM27:%[0-9]+]]:sreg_64_xexec = S_LOAD_DWORDX2_IMM [[COPY]](p4), 216, 0 :: (dereferenceable invariant load (s64), addrspace 4)
+    ; CHECK-NEXT: [[S_LOAD_DWORDX2_IMM28:%[0-9]+]]:sreg_64_xexec = S_LOAD_DWORDX2_IMM [[COPY]](p4), 224, 0 :: (dereferenceable invariant load (s64), align 16, addrspace 4)
+    ; CHECK-NEXT: [[S_LOAD_DWORDX2_IMM29:%[0-9]+]]:sreg_64_xexec = S_LOAD_DWORDX2_IMM [[COPY]](p4), 232, 0 :: (dereferenceable invariant load (s64), addrspace 4)
+    ; CHECK-NEXT: [[S_LOAD_DWORDX2_IMM30:%[0-9]+]]:sreg_64_xexec = S_LOAD_DWORDX2_IMM [[COPY]](p4), 240, 0 :: (dereferenceable invariant load (s64), align 16, addrspace 4)
+    ; CHECK-NEXT: [[S_LOAD_DWORDX2_IMM31:%[0-9]+]]:sreg_64_xexec = S_LOAD_DWORDX2_IMM [[COPY]](p4), 248, 0 :: (dereferenceable invariant load (s64), addrspace 4)
+    ; CHECK-NEXT: [[S_LOAD_DWORDX2_IMM32:%[0-9]+]]:sreg_64_xexec = S_LOAD_DWORDX2_IMM [[COPY]](p4), 256, 0 :: (dereferenceable invariant load (s64), align 16, addrspace 4)
+    ; CHECK-NEXT: [[S_LOAD_DWORDX2_IMM33:%[0-9]+]]:sreg_64_xexec = S_LOAD_DWORDX2_IMM [[COPY]](p4), 264, 0 :: (dereferenceable invariant load (s64), addrspace 4)
+    ; CHECK-NEXT: [[S_LOAD_DWORDX2_IMM34:%[0-9]+]]:sreg_64_xexec = S_LOAD_DWORDX2_IMM [[COPY]](p4), 272, 0 :: (dereferenceable invariant load (s64), align 16, addrspace 4)
+    ; CHECK-NEXT: [[S_LOAD_DWORDX2_IMM35:%[0-9]+]]:sreg_64_xexec = S_LOAD_DWORDX2_IMM [[COPY]](p4), 280, 0 :: (dereferenceable invariant load (s64), addrspace 4)
+    ; CHECK-NEXT: [[S_LOAD_DWORDX2_IMM36:%[0-9]+]]:sreg_64_xexec = S_LOAD_DWORDX2_IMM [[COPY]](p4), 288, 0 :: (dereferenceable invariant load (s64), align 16, addrspace 4)
+    ; CHECK-NEXT: [[S_LOAD_DWORDX2_IMM37:%[0-9]+]]:sreg_64_xexec = S_LOAD_DWORDX2_IMM [[COPY]](p4), 296, 0 :: (dereferenceable invariant load (s64), addrspace 4)
+    ; CHECK-NEXT: [[S_LOAD_DWORDX2_IMM38:%[0-9]+]]:sreg_64_xexec = S_LOAD_DWORDX2_IMM [[COPY]](p4), 304, 0 :: (dereferenceable invariant load (s64), align 16, addrspace 4)
+    ; CHECK-NEXT: [[S_LOAD_DWORDX2_IMM39:%[0-9]+]]:sreg_64_xexec = S_LOAD_DWORDX2_IMM [[COPY]](p4), 312, 0 :: (dereferenceable invariant load (s64), addrspace 4)
+    ; CHECK-NEXT: [[S_LOAD_DWORDX2_IMM40:%[0-9]+]]:sreg_64_xexec = S_LOAD_DWORDX2_IMM [[COPY]](p4), 320, 0 :: (dereferenceable invariant load (s64), align 16, addrspace 4)
+    ; CHECK-NEXT: [[S_LOAD_DWORDX2_IMM41:%[0-9]+]]:sreg_64_xexec = S_LOAD_DWORDX2_IMM [[COPY]](p4), 328, 0 :: (dereferenceable invariant load (s64), addrspace 4)
+    ; CHECK-NEXT: [[S_LOAD_DWORDX2_IMM42:%[0-9]+]]:sreg_64_xexec = S_LOAD_DWORDX2_IMM [[COPY]](p4), 336, 0 :: (dereferenceable invariant load (s64), align 16, addrspace 4)
+    ; CHECK-NEXT: [[S_LOAD_DWORDX2_IMM43:%[0-9]+]]:sreg_64_xexec = S_LOAD_DWORDX2_IMM [[COPY]](p4), 344, 0 :: (dereferenceable invariant load (s64), addrspace 4)
+    ; CHECK-NEXT: [[S_LOAD_DWORDX2_IMM44:%[0-9]+]]:sreg_64_xexec = S_LOAD_DWORDX2_IMM [[COPY]](p4), 352, 0 :: (dereferenceable invariant load (s64), align 16, addrspace 4)
+    ; CHECK-NEXT: [[S_LOAD_DWORDX2_IMM45:%[0-9]+]]:sreg_64_xexec = S_LOAD_DWORDX2_IMM [[COPY]](p4), 360, 0 :: (dereferenceable invariant load (s64), addrspace 4)
+    ; CHECK-NEXT: [[S_LOAD_DWORDX2_IMM46:%[0-9]+]]:sreg_64_xexec = S_LOAD_DWORDX2_IMM [[COPY]](p4), 368, 0 :: (dereferenceable invariant load (s64), align 16, addrspace 4)
+    ; CHECK-NEXT: [[S_LOAD_DWORDX2_IMM47:%[0-9]+]]:sreg_64_xexec = S_...
[truncated]

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arsenm commented Dec 7, 2025

Description should be what the tests are instead of the random PR number

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arsenm reviewed Dec 7, 2025
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This is much too big, and shouldn't be an extraction from the giant original function.

This should be a small, synthetic testcase that shows the effect of considering the offset in the instruction.

llvm/test/CodeGen/AMDGPU/local-stack-alloc-sort-framerefs.mir
@@ -0,0 +1,1093 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx950 -run-pass=localstackalloc -verify-machineinstrs -o - %s | FileCheck %s
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Suggested change
# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx950 -run-pass=localstackalloc -verify-machineinstrs -o - %s | FileCheck %s
# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx950 -run-pass=localstackalloc -o - %s | FileCheck %s

llvm/test/CodeGen/AMDGPU/local-stack-alloc-sort-framerefs.mir

---
name: issue155902
alignment: 1
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Remove all the unnecessary fields

llvm/test/CodeGen/AMDGPU/local-stack-alloc-sort-framerefs.mir
debugInstrRef: false
failsVerification: false
tracksDebugUserValues: false
registers:
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Don't need the registers section

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