[AST][RISCV] Preserve RISC-V intrinsic pragma in AST #171981

4vtomat · 2025-12-12T09:46:37Z

RISC-V vector intrinsic is generated dynamically at runtime, thus it's
note preserved in AST yet when using precompile header, neither do
information in SemaRISCV. We need to write these information to ast
record to be able to use precompile header for RISC-V.

Fixes #109634

RISC-V vector intrinsic is generated dynamically at runtime, thus it's note preserved in AST yet when using precompile header, neither do information in SemaRISCV. We need to write these information to ast record to be able to use precompile header for RISC-V. Fixes llvm#109634

llvmbot · 2025-12-12T09:47:07Z

@llvm/pr-subscribers-clang
@llvm/pr-subscribers-clang-modules

@llvm/pr-subscribers-backend-risc-v

Author: Brandon Wu (4vtomat)

Changes

RISC-V vector intrinsic is generated dynamically at runtime, thus it's
note preserved in AST yet when using precompile header, neither do
information in SemaRISCV. We need to write these information to ast
record to be able to use precompile header for RISC-V.

Fixes #109634

Full diff: https://github.com/llvm/llvm-project/pull/171981.diff

7 Files Affected:

(modified) clang/include/clang/Sema/Sema.h (+1)
(modified) clang/include/clang/Serialization/ASTBitCodes.h (+3)
(modified) clang/include/clang/Serialization/ASTReader.h (+3)
(modified) clang/include/clang/Serialization/ASTWriter.h (+1)
(modified) clang/lib/Serialization/ASTReader.cpp (+14)
(modified) clang/lib/Serialization/ASTWriter.cpp (+11)
(added) clang/test/PCH/riscv-rvv-vectors.c (+14)

diff --git a/clang/include/clang/Sema/Sema.h b/clang/include/clang/Sema/Sema.h
index 97b6bb3d1b3a8..9025fa2e0db92 100644
--- a/clang/include/clang/Sema/Sema.h
+++ b/clang/include/clang/Sema/Sema.h
@@ -66,6 +66,7 @@
 #include "clang/Sema/Scope.h"
 #include "clang/Sema/SemaBase.h"
 #include "clang/Sema/SemaConcept.h"
+#include "clang/Sema/SemaRISCV.h"
 #include "clang/Sema/TypoCorrection.h"
 #include "clang/Sema/Weak.h"
 #include "llvm/ADT/APInt.h"
diff --git a/clang/include/clang/Serialization/ASTBitCodes.h b/clang/include/clang/Serialization/ASTBitCodes.h
index b48f02c601889..5a86d540e5d0b 100644
--- a/clang/include/clang/Serialization/ASTBitCodes.h
+++ b/clang/include/clang/Serialization/ASTBitCodes.h
@@ -745,6 +745,9 @@ enum ASTRecordTypes {
   UPDATE_MODULE_LOCAL_VISIBLE = 76,
 
   UPDATE_TU_LOCAL_VISIBLE = 77,
+
+  /// Record code for #pragma clang riscv intrinsic vector.
+  RISCV_VECTOR_INTRINSICS_PRAGMA = 78,
 };
 
 /// Record types used within a source manager block.
diff --git a/clang/include/clang/Serialization/ASTReader.h b/clang/include/clang/Serialization/ASTReader.h
index d276f0d21b958..63f0fde60bb16 100644
--- a/clang/include/clang/Serialization/ASTReader.h
+++ b/clang/include/clang/Serialization/ASTReader.h
@@ -1079,6 +1079,9 @@ class ASTReader
   /// The IDs of all decls with function effects to be checked.
   SmallVector<GlobalDeclID> DeclsWithEffectsToVerify;
 
+  /// The RISC-V intrinsic pragma(including RVV, SiFive and Andes).
+  SmallVector<bool, 3> RISCVVecIntrinsicPragma;
+
 private:
   struct ImportedSubmodule {
     serialization::SubmoduleID ID;
diff --git a/clang/include/clang/Serialization/ASTWriter.h b/clang/include/clang/Serialization/ASTWriter.h
index c77c98dffc39f..634944fa76c19 100644
--- a/clang/include/clang/Serialization/ASTWriter.h
+++ b/clang/include/clang/Serialization/ASTWriter.h
@@ -640,6 +640,7 @@ class ASTWriter : public ASTDeserializationListener,
   void WriteDeclsWithEffectsToVerify(Sema &SemaRef);
   void WriteModuleFileExtension(Sema &SemaRef,
                                 ModuleFileExtensionWriter &Writer);
+  void WriteRISCVIntrinsicPragmas(Sema &SemaRef);
 
   unsigned DeclParmVarAbbrev = 0;
   unsigned DeclContextLexicalAbbrev = 0;
diff --git a/clang/lib/Serialization/ASTReader.cpp b/clang/lib/Serialization/ASTReader.cpp
index aec61322fb8be..bbf14b6e359a0 100644
--- a/clang/lib/Serialization/ASTReader.cpp
+++ b/clang/lib/Serialization/ASTReader.cpp
@@ -4447,6 +4447,17 @@ llvm::Error ASTReader::ReadASTBlock(ModuleFile &F,
       for (unsigned I = 0, N = Record.size(); I != N; /*in loop*/)
         DeclsToCheckForDeferredDiags.insert(ReadDeclID(F, Record, I));
       break;
+
+    case RISCV_VECTOR_INTRINSICS_PRAGMA: {
+      unsigned NumRecords = Record.back();
+      // Last record which is used to keep number of valid records.
+      if (Record.size() - 1 != NumRecords)
+        return llvm::createStringError(std::errc::illegal_byte_sequence,
+                                       "invalid rvv intrinsic pragma record");
+      for (unsigned i = 0; i < NumRecords; ++i)
+        RISCVVecIntrinsicPragma.push_back(Record[i]);
+      break;
+    }
     }
   }
 }
@@ -9063,6 +9074,9 @@ void ASTReader::UpdateSema() {
         PointersToMembersPragmaLocation);
   }
   SemaObj->CUDA().ForceHostDeviceDepth = ForceHostDeviceDepth;
+  SemaObj->RISCV().DeclareRVVBuiltins = RISCVVecIntrinsicPragma[0];
+  SemaObj->RISCV().DeclareSiFiveVectorBuiltins = RISCVVecIntrinsicPragma[1];
+  SemaObj->RISCV().DeclareAndesVectorBuiltins = RISCVVecIntrinsicPragma[2];
 
   if (PragmaAlignPackCurrentValue) {
     // The bottom of the stack might have a default value. It must be adjusted
diff --git a/clang/lib/Serialization/ASTWriter.cpp b/clang/lib/Serialization/ASTWriter.cpp
index 667e04049dac8..699e45dc08c06 100644
--- a/clang/lib/Serialization/ASTWriter.cpp
+++ b/clang/lib/Serialization/ASTWriter.cpp
@@ -972,6 +972,7 @@ void ASTWriter::WriteBlockInfoBlock() {
   RECORD(PP_ASSUME_NONNULL_LOC);
   RECORD(PP_UNSAFE_BUFFER_USAGE);
   RECORD(VTABLES_TO_EMIT);
+  RECORD(RISCV_VECTOR_INTRINSICS_PRAGMA);
 
   // SourceManager Block.
   BLOCK(SOURCE_MANAGER_BLOCK);
@@ -5232,6 +5233,15 @@ void ASTWriter::WriteModuleFileExtension(Sema &SemaRef,
   Stream.ExitBlock();
 }
 
+void ASTWriter::WriteRISCVIntrinsicPragmas(Sema &SemaRef) {
+  RecordData Record;
+  Record.push_back(SemaRef.RISCV().DeclareRVVBuiltins);
+  Record.push_back(SemaRef.RISCV().DeclareSiFiveVectorBuiltins);
+  Record.push_back(SemaRef.RISCV().DeclareAndesVectorBuiltins);
+  Record.push_back(Record.size());
+  Stream.EmitRecord(RISCV_VECTOR_INTRINSICS_PRAGMA, Record);
+}
+
 //===----------------------------------------------------------------------===//
 // General Serialization Routines
 //===----------------------------------------------------------------------===//
@@ -6130,6 +6140,7 @@ ASTFileSignature ASTWriter::WriteASTCore(Sema *SemaPtr, StringRef isysroot,
     WriteFPPragmaOptions(SemaPtr->CurFPFeatureOverrides());
     WriteOpenCLExtensions(*SemaPtr);
     WriteCUDAPragmas(*SemaPtr);
+    WriteRISCVIntrinsicPragmas(*SemaPtr);
   }
 
   // If we're emitting a module, write out the submodule information.
diff --git a/clang/test/PCH/riscv-rvv-vectors.c b/clang/test/PCH/riscv-rvv-vectors.c
new file mode 100644
index 0000000000000..30f058753c747
--- /dev/null
+++ b/clang/test/PCH/riscv-rvv-vectors.c
@@ -0,0 +1,14 @@
+// RUN: %clang_cc1 -triple riscv64-linux-gnu -target-feature +v -emit-pch -o %t %s
+// RUN: %clang_cc1 -triple riscv64-linux-gnu -target-feature +v -include-pch %t \
+// RUN:   -fsyntax-only -verify %s
+
+// expected-no-diagnostics
+
+#ifndef HEADER
+#define HEADER
+#include <riscv_vector.h>
+#else
+vuint64m4_t v_add(vuint64m4_t a, vuint64m4_t b, size_t vl) {
+    return __riscv_vadd_vv_u64m4(a, b, vl);
+}
+#endif

topperc · 2025-12-12T17:07:35Z

clang/lib/Serialization/ASTWriter.cpp

+  Record.push_back(SemaRef.RISCV().DeclareRVVBuiltins);
+  Record.push_back(SemaRef.RISCV().DeclareSiFiveVectorBuiltins);
+  Record.push_back(SemaRef.RISCV().DeclareAndesVectorBuiltins);
+  Record.push_back(Record.size());


Why is the size pushed last? Why not first?

I was thinking it has less complexity than insert to front. However I think we can just hard code it since we have to update this file anyway when we have new intrinsic class to update lol

clang/lib/Serialization/ASTReader.cpp

github-actions · 2025-12-13T05:34:16Z

✅ With the latest revision this PR passed the C/C++ code formatter.

github-actions · 2025-12-13T06:04:46Z

🐧 Linux x64 Test Results

112102 tests passed
4520 tests skipped

✅ The build succeeded and all tests passed.

topperc

LGTM

llvm-ci · 2025-12-17T05:05:02Z

LLVM Buildbot has detected a new failure on builder llvm-clang-x86_64-sie-ubuntu-fast running on sie-linux-worker while building clang at step 6 "test-build-unified-tree-check-all".

Full details are available at: https://lab.llvm.org/buildbot/#/builders/144/builds/42454