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@kaolpr kaolpr commented Sep 1, 2022

Uses m-labs/migen#264

  • ported S7 RGMII from LiteEth
  • modified SPI flash core to support 1x non-IO SPI flash (had problems with x4 IO operation)
  • added Digilent Genesys 2 target

kaolpr added a commit to Technosystem-Labs/artiq that referenced this pull request Sep 1, 2022
kaolpr added a commit to Technosystem-Labs/artiq that referenced this pull request Sep 1, 2022
kaolpr added a commit to Technosystem-Labs/artiq that referenced this pull request Sep 1, 2022


def main():
parser = argparse.ArgumentParser(description="MiSoC port to the KC705")
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It's not KC705.

@sbourdeauducq
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Please split into three commits.

@sbourdeauducq
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  • had problems with x4 IO operation

Why?

@kaolpr
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kaolpr commented Sep 28, 2022

  • had problems with x4 IO operation

Why?

Had no time to debug. Reducing to 1x non-IO worked. I do have it on my TODO list, but with low priority.

kaolpr added a commit to Technosystem-Labs/artiq that referenced this pull request Jan 16, 2023
#!/usr/bin/env python3

#
# This file is based on LiteX-Boards Digilent Genesys 2 target.
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Yeah, itself based on code that I wrote 10-11 years ago and which changed remarkably little since...

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2 participants