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trim a little more
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makslevental committed Sep 28, 2022
1 parent a26f78b commit cf99916
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Showing 3 changed files with 9 additions and 10 deletions.
16 changes: 8 additions & 8 deletions examples/braggnn.py
Original file line number Diff line number Diff line change
Expand Up @@ -13,10 +13,10 @@
class Part1(torch.nn.Module):
def __init__(self):
super().__init__()
self.cnn_layers_1 = Conv2d(1, 15, kernel_size=(3, 3), stride=(1, 1))
self.theta_layer = Conv2d(15, 8, kernel_size=(1, 1), stride=(1, 1))
self.phi_layer = Conv2d(15, 8, kernel_size=(1, 1), stride=(1, 1))
self.g_layer = Conv2d(15, 8, kernel_size=(1, 1), stride=(1, 1))
self.cnn_layers_1 = Conv2d(1, 14, kernel_size=(3, 3), stride=(1, 1))
self.theta_layer = Conv2d(14, 8, kernel_size=(1, 1), stride=(1, 1))
self.phi_layer = Conv2d(14, 8, kernel_size=(1, 1), stride=(1, 1))
self.g_layer = Conv2d(14, 8, kernel_size=(1, 1), stride=(1, 1))
self.soft = SoftMax()

def forward(self, inp):
Expand All @@ -37,10 +37,10 @@ def forward(self, inp):
class Part2(torch.nn.Module):
def __init__(self):
super().__init__()
self.out_cnn = Conv2d(8, 15, kernel_size=(1, 1), stride=(1, 1))
self.out_cnn = Conv2d(8, 14, kernel_size=(1, 1), stride=(1, 1))
self.cnn_layers_2 = Sequential(
ReLU(),
Conv2d(15, 8, kernel_size=(3, 3), stride=(1, 1)),
Conv2d(14, 8, kernel_size=(3, 3), stride=(1, 1)),
ReLU(),
)

Expand Down Expand Up @@ -218,14 +218,14 @@ def make_braggn_part2(scale, img_size=11, simplify_weights=True):
mod.apply(set_weights)
z = mod(
torch.randn(1, 8, img_size - 2, img_size - 2),
torch.randn(1, 15, img_size - 2, img_size - 2),
torch.randn(1, 14, img_size - 2, img_size - 2),
)
print(z.shape)
mlir_module = compile_nn_module_to_mlir(
mod,
[
([1, 8, img_size - 2, img_size - 2], torch.float32),
([1, 15, img_size - 2, img_size - 2], torch.float32),
([1, 14, img_size - 2, img_size - 2], torch.float32),
],
)
return str(mlir_module)
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2 changes: 1 addition & 1 deletion scripts/make_braggnn_parts_top.py
Original file line number Diff line number Diff line change
Expand Up @@ -7,7 +7,7 @@
signal_width = 12
num_tdm_wires = 0
num_mux_to_demux = 20
stub_inputs = True
stub_inputs = False


class CombOrSeq(enum.Enum):
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1 change: 0 additions & 1 deletion scripts/vivado_alt_synth.tcl
Original file line number Diff line number Diff line change
Expand Up @@ -53,7 +53,6 @@ report_methodology -file ${reports_dir}/post_synth/methodology.rpt

puts "\n================================( Place Design )================================="

#set_property ALLOW_COMBINATORIAL_LOOPS TRUE [get_nets -regexp .*]
#eval place_design -directive SSI_SpreadLogic_high -ultrathreads -fanout_opt
eval place_design -ultrathreads -fanout_opt

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