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maze1377 committed Jul 6, 2019
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29 changes: 29 additions & 0 deletions ALU.v
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module ALU(input [31:0] data1,data2,input [3:0] aluoperation,output reg [31:0] result,output reg zero,lt,gt);
always@(aluoperation,data1,data2)
begin
case (aluoperation)
4'b0000 : result = data1 + data2; // ADD
4'b0001 : result = data1 - data2; // SUB
4'b0010 : result = data1 & data2; // AND
4'b0011 : result = data1 | data2; // OR
4'b0100 : result = data1 ^ data2; // XOR
4'b0101 : result = {31'b0,lt};//slt

default : result = data1 + data2; // ADD
endcase
if(data1>data2)
begin
gt = 1'b1;
lt = 1'b0;
end else if(data1<data2)
begin
gt = 1'b0;
lt = 1'b1;
end

if (result==32'd0) zero=1'b1;
else zero=1'b0;
end

endmodule

23 changes: 23 additions & 0 deletions ALUcontrol.v
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module ALUcontrol(clk,funct,ALUOp,ALUsignal);
input clk;
input[5:0] funct;
input[2:0] ALUOp;
output[3:0] ALUsignal;
reg[3:0] ALUsignal;
always@(funct , ALUOp ,posedge clk)begin
case(ALUOp)
3'b010:case(funct)
6'b100000:ALUsignal=4'b00;//add
6'b100010:ALUsignal=4'b01;//sub
6'b100100:ALUsignal=4'b10;//and
6'b100101:ALUsignal=4'b11;//or
6'b101010:ALUsignal=4'b101;//stl
endcase
3'b001:ALUsignal=4'b0001;//branch
3'b000:ALUsignal=4'b0000;//Lw and sw
3'b011:ALUsignal=4'b0010;//andi
3'b100:ALUsignal=4'b0011;//ori
3'b111:ALUsignal=4'b0101; //slti
endcase
end
endmodule
53 changes: 53 additions & 0 deletions Controlstall.v
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module Controlstall(clk,op1,op2,op3,stall);
input [5:0]op1,op2,op3;
input clk;
output reg stall;
initial begin
stall=1'b1;
end
always @(posedge clk)begin


if(op1==6'b000100 | op1==6'b000101 | op1==6'b000010)begin// beq or bne or j
stall=1'b0;
end
if(op2==6'b000100 | op2==6'b000101 | op2==6'b000010)begin// beq or bne or j
stall=1'b0;
end
if(op3==6'b000100 | op3==6'b000101 | op3==6'b000010)begin// beq or bne or j
stall=1'b0;
end
else begin
stall=1'b1;
end

end


endmodule

module nopSet(clk,s1,s2,oldF,oldD,newF,newD);
input clk,s1,s2;
input [31:0] oldF,oldD;
output reg[31:0]newD,newF;

initial begin
end
always @(posedge clk)begin
if(s1==1'b0 && s2==1'b0)begin
newF=32'b0;
newD=32'b0;
end
else if(s1==1'b0 && s2==1'b1)begin
newD=32'b0;
end
else if(s1==1'b1 && s2==1'b0)begin
newF=32'b0;
end
else
begin
newD=oldD;
newF=oldF;
end
end
endmodule
27 changes: 27 additions & 0 deletions DM.v
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module DMemBank(input memread, input memwrite, input [31:0] address, input [31:0] writedata, output reg [31:0] readdata);

reg [31:0] mem_array [127:0];
wire[6:0]finalAddress;
assign finalAddress=address[8:0];
integer i;
initial
begin
for (i=0; i<127; i=i+1)
mem_array[i]=i*10;
end

always@(memread, memwrite, address, mem_array[address], writedata)
begin
if(memread)begin
readdata=mem_array[finalAddress];
end

if(memwrite)
begin
mem_array[finalAddress]= writedata;
end

end

endmodule

48 changes: 48 additions & 0 deletions EXMEM.v
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module EXMEM(clock,iRegDests,iRegWrite,iALUSrc,iMemRead,iMemWrite,iMemToReg,iBranchs,iJumps,iALUCtrl,
iIR,iPC,iB,iResult,iRegDest,iBranch,iJump,iZero,
oRegDests,oRegWrite,oALUSrc,oMemRead,oMemWrite,oMemToReg,oBranchs,oJumps,oALUCtrl,
oIR,oPC,oB,oResult,oRegDest,oBranch,oJump,oZero,enable);
input [31:0] iIR,iPC,iB,iResult,iBranch,iJump;
input iZero,clock,enable;
input iRegDests,iRegWrite,iALUSrc,iMemRead,iMemWrite,iMemToReg,iBranchs,iJumps;
input [3:0]iALUCtrl;
input [4:0] iRegDest;
output [31:0] oIR,oPC,oB,oResult,oBranch,oJump;
output oZero;
output oRegDests,oRegWrite,oALUSrc,oMemRead,oMemWrite,oMemToReg,oBranchs,oJumps;
output [3:0]oALUCtrl;
output [4:0]oRegDest;
reg [31:0] oIR,oPC,oB,oResult,oBranch,oJump;
reg oZero;
reg oRegDests,oRegWrite,oALUSrc,oMemRead,oMemWrite,oMemToReg,oBranchs,oJumps;
reg [3:0]oALUCtrl;
reg [4:0]oRegDest;
initial begin
oPC=32'b0;
oIR=32'b0;
end
always @(posedge clock)
begin
if(enable)begin
oRegDests<=iRegDests;
oRegWrite<=iRegWrite;
oALUSrc<=iALUSrc;
oMemRead<=iMemRead;
oMemWrite<=iMemWrite;
oMemToReg<=iMemToReg;
oBranchs<=iBranchs;
oJumps<=iJumps;
oALUCtrl<=iALUCtrl;
oIR<=iIR;
oPC<=iPC;
oB<=iB;
oResult<=iResult;
oRegDest<=iRegDest;
oBranch<=iBranch;
oJump<=iJump;
oZero<=iZero;
end
end
endmodule


46 changes: 46 additions & 0 deletions IDEX.v
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module IDEX(clock,iRegDests,iRegWrite,iALUSrc,iMemRead,iMemWrite,iMemToReg,iBranchs,iJumps,iALUCtrl,
iIR,iPC,iA,iB,iRegDest,iBranch,iJump,
oRegDests,oRegWrite,oALUSrc,oMemRead,oMemWrite,oMemToReg,oBranchs,oJumps,oALUCtrl,
oIR,oPC,oA,oB,oRegDest,oBranch,oJump,enable);
input [31:0] iIR,iPC,iA,iB,iBranch,iJump;
input clock,enable;
input iRegDests,iRegWrite,iALUSrc,iMemRead,iMemWrite,iMemToReg,iBranchs,iJumps;
input [3:0]iALUCtrl;
input [4:0] iRegDest;
output [31:0] oIR,oPC,oA,oB,oBranch,oJump;
output oRegDests,oRegWrite,oALUSrc,oMemRead,oMemWrite,oMemToReg,oBranchs,oJumps;
output [3:0]oALUCtrl;
output [4:0]oRegDest;
reg [31:0] oIR,oPC,oA,oB,oResult,oBranch,oJump;
reg oZero;
reg oRegDests,oRegWrite,oALUSrc,oMemRead,oMemWrite,oMemToReg,oBranchs,oJumps;
reg [3:0]oALUCtrl;
reg [4:0]oRegDest;
initial begin
oPC=32'b0;
oIR=32'b0;
end
always @(posedge clock)
begin
if(enable)begin
oRegDests<=iRegDests;
oRegWrite<=iRegWrite;
oALUSrc<=iALUSrc;
oMemRead<=iMemRead;
oMemWrite<=iMemWrite;
oMemToReg<=iMemToReg;
oBranchs<=iBranchs;
oJumps<=iJumps;
oALUCtrl<=iALUCtrl;
oIR<=iIR;
oPC<=iPC;
oA<=iA;
oB<=iB;
oRegDest<=iRegDest;
oBranch<=iBranch;
oJump<=iJump;
end
end
endmodule

101 changes: 101 additions & 0 deletions InstMem.v
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module IMemBank(input memread, input [31:0] address, output reg [31:0] readdata);

reg [31:0] mem_array [255:0];
reg [31:0]temp;
integer i;
initial begin
for (i=11; i<255; i=i+1)
begin
mem_array[i]=32'b0;
end
end
always@(memread, address, mem_array[address])
begin
if(memread)begin
temp=address>>2;
readdata=mem_array[temp];
end
//////////////////////////////////////////////////////////////////////////////////////////////////////// test bench!
//lvl 1
/*mem_array[0]={6'b0,5'b10,5'b1,5'b11,5'b0,6'b100000};//add reg3,reg2,reg1 =30
mem_array[1]={6'b0,5'b10,5'b1,5'b100,5'b0,6'b100010};//sub reg4,reg2,reg1 =10
mem_array[2]={6'b0,5'b10,5'b1,5'b101,5'b0,6'b100101};//or reg5,reg2,reg1 =30
mem_array[3]={6'b0,5'b10,5'b1,5'b110,5'b0,6'b100100};//and reg6,reg2,reg1 =0
mem_array[4]={6'b0,5'b10,5'b1,5'b111,5'b0,6'b101010};//stl reg7,reg2,reg1 =0
mem_array[5]={6'b001000,5'b10,5'b1000,16'b1010};//addi r8,r2,10 =30
mem_array[6]={6'b001010,5'b10,5'b1001,16'b1010};//slti r9,r2,10 =0
mem_array[7]={6'b001101,5'b10,5'b1010,16'b1010};//ori r10,r2,10 =30
mem_array[8]={6'b001100,5'b10,5'b1011,16'b1010};//andi r11,r2,10 =0
mem_array[9]={6'b101011,5'b10,5'b0,16'b1};//sw reg0,1(reg2) =mem[21]<=0
mem_array[10]={6'b100011,5'b0,5'b1100,16'b0};//lw reg12,0(reg0) =reg[12]<=0
*/
/////////////////////////////////////////////////////////////////////////////////////////////////////////////
//lvl 2
/*mem_array[0]={6'b0,5'b10,5'b1,5'b11,5'b0,6'b100000};//add reg3,reg2,reg1 =30
mem_array[1]={6'b0,5'b11,5'b1,5'b100,5'b0,6'b100010};//sub reg4,reg3,reg1 =20
mem_array[2]={6'b0,5'b100,5'b1,5'b101,5'b0,6'b100101};//or reg5,reg4,reg1 =30
mem_array[3]={6'b0,5'b10,5'b1,5'b110,5'b0,6'b100100};//and reg6,reg2,reg1 =0
mem_array[4]={6'b0,5'b10,5'b1,5'b111,5'b0,6'b101010};//stl reg7,reg2,reg1 =0
mem_array[5]={6'b001000,5'b10,5'b1000,16'b1010};//addi r8,r2,10 =30
mem_array[6]={6'b001010,5'b1000,5'b1001,16'b1000000};//slti r9,r8,32 =1
mem_array[7]={6'b001101,5'b10,5'b1010,16'b1010};//ori r10,r2,10 =30
mem_array[8]={6'b001100,5'b1001,5'b1011,16'b1010};//andi r11,r9,10 =0
mem_array[9]={6'b101011,5'b1010,5'b1011,16'b1};//sw reg11,1(reg10) =mem[31]<=0
mem_array[10]={6'b100011,5'b1010,5'b1100,16'b01};//lw reg12,1(reg10) =reg[12]<=0*/
///////////////////////////////////////////////////////////////////////////////////////////////////////////
//lvl 3
// mem_array[0]={6'b0,5'b10,5'b1,5'b11,5'b0,6'b100000};//add reg3,reg2,reg1 =30
// mem_array[1]={6'b0,5'b11,5'b1,5'b100,5'b0,6'b100010};//sub reg4,reg3,reg1 =20
// mem_array[2]={6'b0,5'b100,5'b1,5'b101,5'b0,6'b100101};//or reg5,reg4,reg1 =30

// mem_array[3]={6'b100,5'b100,5'b101,16'b10};//beq r4,r5,2ta

// mem_array[4]={6'b0,5'b10,5'b1,5'b110,5'b0,6'b100100};//and reg6,reg2,reg1 =0

// mem_array[5]={6'b101,5'b110,5'b101,16'b1000};//bne r6,r5,2ta

// mem_array[6]={6'b0,5'b10,5'b1,5'b111,5'b0,6'b101010};//stl reg7,reg2,reg1 =0

// mem_array[7]={6'b10,26'b100};//jump lable4 13 ya 14

// mem_array[8]={6'b001000,5'b10,5'b1000,16'b1010};//addi r8,r2,10 =30
// mem_array[9]={6'b001010,5'b1000,5'b1001,16'b1000000};//slti r9,r8,32 =1
// mem_array[10]={6'b001101,5'b10,5'b1010,16'b1010};//ori r10,r2,10 =30
// mem_array[11]={6'b001100,5'b1001,5'b1011,16'b1010};//andi r11,r9,10 =0

// mem_array[12]={6'b101011,5'b1010,5'b1011,16'b1};//sw reg11,1(reg10) =mem[31]<=0
// mem_array[13]={6'b100011,5'b1010,5'b1100,16'b01};//lw reg12,1(reg10) =reg[12]<=0


/*
//r2=max , r3=min , r4=1 , r5=i , r6=adress , r7=current
mem_array[0]={6'b001000,5'b0,5'b10,16'b1010};//addi r2,r0,10
mem_array[1]={6'b001000,5'b0,5'b11,16'b1010};//addi r3,r0,10
mem_array[2]={6'b001000,5'b0,5'b100,16'b1};//addi r4,r0,1
mem_array[3]={6'b001000,5'b0,5'b101,16'b1};//addi r5,r0,1
//loop:
mem_array[4]={6'b0,5'b0,5'b00101,5'b00110,11'b0};//add r6,r0,r5
mem_array[5]={6'b100011,5'b00110,5'b00111,16'b0};//lw r7,0(r6)
mem_array[6]={6'b0,5'b10,5'b111,5'b01000,5'b0,6'b101010};//slt r8,r7,r2
mem_array[7]={6'b100,5'b1000,5'b0,16'b10};//beq r8,r0,lable1
mem_array[8]={6'b10,26'b1010};//jump lable2 adrese 9 ya 8
//lable1
mem_array[9]={6'b1000,5'b111,5'b10,16'b0};//addi r2,r7,0
//lable2:
mem_array[10]={6'b0,5'b11,5'b111,5'b1000,5'b0,6'b101010};//slt r8,r3,r7
mem_array[11]={6'b100,5'b1000,5'b0,16'b10};//beq r8,r0,lable3
mem_array[12]={6'b10,26'b1110};//jump lable4 13 ya 14
//lable3:
mem_array[13]={6'b1000,5'b111,5'b11,16'b0};//addi r3,r7,0
//lable4
mem_array[14]={6'b1000,5'b101,5'b101,16'b1};//addi r5,r5,1
mem_array[15]={6'b1010,5'b100,5'b1001,16'b1011};//slti r9,r5,11
mem_array[16]={6'b100,5'b1001,5'b100,16'b1111111111110100};//beq r9,r4,loop
*/
end
endmodule

40 changes: 40 additions & 0 deletions MEMWB.v
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module MEMWB(clock,iRegDests,iRegWrite,iALUSrc,iMemRead,iMemWrite,iMemToReg,iBranchs,iJumps,iALUCtrl,
iIR,iB,iResult,iRegDest,
oRegDests,oRegWrite,oALUSrc,oMemRead,oMemWrite,oMemToReg,oBranchs,oJumps,oALUCtrl,
oIR,oB,oResult,oRegDest,enable);
input [31:0] iIR,iB,iResult;
input clock,enable;
input iRegDests,iRegWrite,iALUSrc,iMemRead,iMemWrite,iMemToReg,iBranchs,iJumps;
input [3:0]iALUCtrl;
input [4:0] iRegDest;
output [31:0] oIR,oB,oResult;
output oRegDests,oRegWrite,oALUSrc,oMemRead,oMemWrite,oMemToReg,oBranchs,oJumps;
output [3:0]oALUCtrl;
output [4:0]oRegDest;
reg [31:0] oIR,oB,oResult;
reg oRegDests,oRegWrite,oALUSrc,oMemRead,oMemWrite,oMemToReg,oBranchs,oJumps;
reg [3:0]oALUCtrl;
reg [4:0]oRegDest;
initial begin
oIR=32'b0;
end
always @(posedge clock)
begin
if(enable)begin
oRegDests<=iRegDests;
oRegWrite<=iRegWrite;
oALUSrc<=iALUSrc;
oMemRead<=iMemRead;
oMemWrite<=iMemWrite;
oMemToReg<=iMemToReg;
oBranchs<=iBranchs;
oJumps<=iJumps;
oALUCtrl<=iALUCtrl;
oIR<=iIR;
oB<=iB;
oResult<=iResult;
oRegDest<=iRegDest;
end
end
endmodule

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