The hardware description of a simple vector processor. A Verilog project for the Digital Systems Design course, Spring 2024.
- Verilog
- ModelSim
This project aims to design a vector processor capable of processing multiple words simultanously. The difference of this approach, as opposed to normal processors, can be seen below:
In this design, a modular approach was taken by breaking the Vector Processor into three main modules: a register file, an ALU, and a memory. The Vector processor was, then, described by putting these modules together.
A thorough and detailed explanation of the implementation of this project can be found in the Documents directory.
The simulation of the hardware description provided in this project can be done with ModelSim: an enviroment for simulation of hardware description languages such as Verilog, which was used in this project.
The module code -> q7 -> VectorProcessor.v has been specifically designed to instantiate the vector processor and run many tests on it. All tests will be run automatically by pressing the simulate button in ModelSim and choosing the aforementioned module in the window that pops up.
The tests have been designed to be thorough and cover many cases, such as everyday use case scenarios, and also edge cases. They are formatted in three classes: 1.Normal tests; 2.Edge cases, such as very large or very small numbers; and 3.Randomly generated tests.
After a successful simulation run under the default testbench, ModelSim should display the following:
The report in Documents->Extra-Report delves into the details of this simulation, what it means, how to read its results and why they make sense, and how the functionality of the described vector processor is practically proven by its testbench.