430.315a

@SNU, 2022

FPGA Verification : Nexys4 DDR Board(Artix-7 Based FPGA)

Design UART Communication(Asynchronous) considering Metastability Issues

[Metastabitlity Issue]

• Problems with asynchronous data transfer
• Capturing a value when the data is not stable sometimes leaves a half-way value other than 0 and 1

[Common Solution]

• Perform buffering with multiple flip-flops
• Usually, the value becomes stable to 0 or 1 after a certain period of time
• Reduce the probability of metastability through buffering

[UART Communication]

[Result]

Design Fully Connected Layer in CNN for Image Classification

[Fully Connected Layer]

• FC Layer in CNN for Image Classification
• Generally at the end of the network
• Classify images through features extracted by the convolution layer.

[Architectue of the Module]

[Result]

Design CNN(Conv2d Layers) Image Classifier Accerlerator

[Image Classifier Accelerator]

[Architecture of the Module]

[Result]