CA-lab

MIPS implementation with verilog in Computer Architecture Lab.

Name		Name	Last commit message	Last commit date
Latest commit History 21 Commits
.gitignore		.gitignore
ALU.v		ALU.v
AddressMapping.v		AddressMapping.v
Cache.stp		Cache.stp
Cache_Controller.v		Cache_Controller.v
ConditionCheck.v		ConditionCheck.v
ControlUnit.v		ControlUnit.v
EXE.v		EXE.v
EXE_MEM_REG.v		EXE_MEM_REG.v
Forward.stp		Forward.stp
Forward.v		Forward.v
Forward_auto_stripped.stp		Forward_auto_stripped.stp
HazardDetection.v		HazardDetection.v
ID.v		ID.v
ID_EXE_REG.v		ID_EXE_REG.v
IF.v		IF.v
IF_ID_REG.v		IF_ID_REG.v
MEM.v		MEM.v
MEM_WB_REG.v		MEM_WB_REG.v
MIPS.V		MIPS.V
MUX2.v		MUX2.v
MUX32.v		MUX32.v
MUX32_4.v		MUX32_4.v
MUX5.v		MUX5.v
MUX9.v		MUX9.v
Memory.v		Memory.v
README.md		README.md
ROM.v		ROM.v
Register32.v		Register32.v
RegisterFile.v		RegisterFile.v
SRAM.stp		SRAM.stp
SRAM_AddressMapping.v		SRAM_AddressMapping.v
SRAM_Controller.v		SRAM_Controller.v
SRAM_auto_stripped.stp		SRAM_auto_stripped.stp
SevenSegment.v		SevenSegment.v
SignExtend.v		SignExtend.v
TestBench.v		TestBench.v
WB.v		WB.v
benchmark.v		benchmark.v
mips-nope.png		mips-nope.png
stp1.stp		stp1.stp
stp1_auto_stripped.stp		stp1_auto_stripped.stp

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