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Initial support for using peano with AIE2P (strix). #1071

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merged 6 commits into from
Feb 4, 2025
Merged

Initial support for using peano with AIE2P (strix). #1071

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1 change: 0 additions & 1 deletion compiler/plugins/target/AMD-AIE/aie/AMDAIECoreToStandard.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -7,7 +7,6 @@
#include "AIEDialect.h"
#include "Passes.h"
#include "mlir/Conversion/FuncToLLVM/ConvertFuncToLLVM.h"
#include "mlir/Conversion/FuncToLLVM/ConvertFuncToLLVMPass.h"
#include "mlir/Dialect/Arith/IR/Arith.h"
#include "mlir/Dialect/LLVMIR/LLVMDialect.h"
#include "mlir/IR/Attributes.h"
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2 changes: 1 addition & 1 deletion compiler/plugins/target/AMD-AIE/aievec/AIEVecDialect.h
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Expand Up @@ -16,6 +16,6 @@
#include "mlir/IR/Dialect.h"

#define GET_OP_CLASSES
#include "aievec/AIEVecOpsDialect.h.inc"
#include "aievec/AIEVecDialect.h.inc"

#endif // AIE_DIALECT_AIEVEC_IR_AIEVECDIALECT_H
2 changes: 1 addition & 1 deletion compiler/plugins/target/AMD-AIE/aievec/AIEVecOps.cpp
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Expand Up @@ -24,8 +24,8 @@ using namespace mlir;
using namespace mlir::iree_compiler;
using namespace mlir::iree_compiler::aievec;

#include "aievec/AIEVecDialect.cpp.inc"
#include "aievec/AIEVecEnums.cpp.inc"
#include "aievec/AIEVecOpsDialect.cpp.inc"

//===----------------------------------------------------------------------===//
// AIEVecDialect
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1 change: 1 addition & 0 deletions compiler/plugins/target/AMD-AIE/aievec/AIEVecOps.h
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Expand Up @@ -13,6 +13,7 @@
#ifndef AIE_DIALECT_AIEVEC_IR_AIEVECOPS_H
#define AIE_DIALECT_AIEVEC_IR_AIEVECOPS_H

#include "iree-amd-aie/aie_runtime/AMDAIEEnums.h"
#include "mlir/Bytecode/BytecodeOpInterface.h"
#include "mlir/Interfaces/InferTypeOpInterface.h"
#include "mlir/Interfaces/SideEffectInterfaces.h"
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63 changes: 33 additions & 30 deletions compiler/plugins/target/AMD-AIE/aievec/AIEVecOps.td
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Expand Up @@ -13,12 +13,12 @@
#ifndef AIEVEC_OPS
#define AIEVEC_OPS

// include "aie/Dialect/AIE/IR/AIEAttrs.td"
include "AIEVecDialect.td"
include "AIEVecAttributes.td"
include "AIEVecTypeConstraints.td"

include "mlir/Interfaces/InferTypeOpInterface.td"
include "mlir/Interfaces/SideEffectInterfaces.td"
include "iree-amd-aie/aie_runtime/AMDAIEEnums.td"

// Base class for AIE dialect ops.
class AIEVec_Op<string mnemonic, list<Trait> traits = []> :
Expand Down Expand Up @@ -58,7 +58,6 @@ def AIEVec_ExtOp:
Pure
]>,
Arguments<(ins AnyVectorOfNonZeroRank:$source,
// ConfinedAttr<AIEI8Attr, [IntMinValue<0>, IntMaxValue<8>]>:$index)>,
ConfinedAttr<I8Attr, [IntMinValue<0>, IntMaxValue<8>]>:$index)>,
Results<(outs AnyVectorOfNonZeroRank:$result)> {
let summary = "AIE ext";
Expand Down Expand Up @@ -130,39 +129,43 @@ def AIEVec_SRSOp:
}

def AIEVec_MatMulOp:
AIEVec_Op<"matmul", [
Pure,
AllRanksMatch<["lhs", "rhs", "acc"]>,
AllTypesMatch<["acc", "result"]>,
ShapesCompatibleWithContraction<"lhs", "rhs", "acc">,
IsValidAIE2MatMulShapeAndType<"lhs", "rhs", "acc">
]>,
Arguments<(ins AIE2MatMulLHS:$lhs,
AIE2MatMulRHS:$rhs,
AIE2MatMulACC:$acc)>,
Results<(outs AIE2MatMulACC:$result)> {
let summary = "AIE2 matrix-multiply and accummulate";
AIEVec_Op<"matmul", [Pure, AllTypesMatch<["acc", "result"]>]>,
Arguments<(ins AnyVectorOfNonZeroRank:$lhs,
AnyVectorOfNonZeroRank:$rhs,
AnyVectorOfNonZeroRank:$acc)>,
Results<(outs AnyVectorOfNonZeroRank:$result)> {
let summary = "AIE matrix-multiply and accummulate";
let description = [{
AMD AIEv2-specific intrinsic that performs a matrix multiplications
AMD AIE-specific intrinsic that performs a matrix multiplications
between `lhs` and `rhs`, and accumulates the result in `acc`.

Currently, this intrinsic supports the following type combinations:

lhs | rhs | Accumulator
:------------------:|:------------------:|:-----------------:
`vector<4x16xi8>` | `vector<16x8xi4>` | `vector<4x8xi32>`
`vector<4x8xi8>` | `vector<8x8xi8>` | `vector<4x8xi32>`
`vector<4x4xi16>` | `vector<4x8xi8>` | `vector<4x8xi32>`
`vector<4x2xi16>` | `vector<2x8xi16>` | `vector<4x8xi32>`
`vector<2x8xi16>` | `vector<8x8xi8>` | `vector<2x8xi64>`
`vector<4x8xi16>` | `vector<8x4xi8>` | `vector<4x4xi64>`
`vector<2x4xi16>` | `vector<4x8xi16>` | `vector<2x8xi64>`
`vector<4x4xi16>` | `vector<4x4xi16>` | `vector<4x4xi64>`
`vector<4x2xi32>` | `vector<2x4xi16>` | `vector<4x4xi64>`
`vector<4x8xbf16>` | `vector<8x4xbf16>` | `vector<4x4xf32>`
Currently, this intrinsic supports the following type combinations
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A few XLLVM ops are removed: we don't use broadcast or a few others, so I've trimmed the set of ops we support down.

Why though? Can't we just keep supporting them?

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Just to check: are you referring to the reduced set of AIE2 matmuls supported, the removal of ops we don't use (like broadcast) or both?

The code and ops I've removed is not tested (here or in mlir-aie afaict), not reachable through the compiler currently, and is kind of just a burden to maintain. I don't see any harm in removing it, we can add it back with tests when we need to.

for aie2 (phoenix):

lhs | rhs | Accumulator
:------------------:|:------------------:|:-----------------:
`vector<4x8xi8>` | `vector<8x8xi8>` | `vector<4x8xi32>`
`vector<4x8xbf16>` | `vector<8x4xbf16>` | `vector<4x4xf32>`

for aie2P (strix):

lhs | rhs | Accumulator
:------------------:|:------------------:|:-----------------:
`vector<8x8xi8>` | `vector<8x8xi8>` | `vector<8x8xi32>`

These types are checked in `verifyOperands`.
}];
let assemblyFormat = [{$lhs `,` $rhs `,` $acc attr-dict `:` type($lhs) `,`
type($rhs) `into` type($acc)}];

let extraClassDeclaration = [{
static bool verifyOperands(
Type lhs, Type rhs, Type acc, AMDAIE::AMDAIEDevice);
}];

// As the supported types are device dependent, verification needs to have
// the device type. The `verifyOperands` function should be called when
// the device type is available.
let hasVerifier = 0;
}

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