Specified clk input/outputs

[ChucklesOnGitHub]

addresses #120

[ChucklesOnGitHub]

Actually, specififying this at the level of the breakout board is not correct.
The PCIe controller clock port implementation is what needs to be specified:

However, it might be useful to constrain this in the documentation and ask users to connect the breakout board and the controller in a fixed way such as Clk0 - In0, Clk1 - In1, Clk2 - O1.

[cjsha]

Actually, specififying this at the level of the breakout board is not correct.

Agreed.

it might be useful to constrain this in the documentation and ask users to connect the breakout board and the controller in a fixed way such as Clk0 - In0, Clk1 - In1, Clk2 - O1.

I think later versions of the bracket for the pcie controller have different labels than the 3D printed version shown in the photo you posted,

but I agree regardless that what you suggest here would be helpful for anyone with the older version.

[cjsha]

I made some changes to address your comments and also updated the list of compatible headstages for breakout board & pcie host.

[ChucklesOnGitHub]

I've made some more edits. Maybe they are a bit of a stretch. But my beef with how things are is that it is hard to understand all the connectivity and capatibilities from a single page/pic. And I understand that the bb is providing access to functionality that is ultimately on the controller, but the user sees the bb.. the controller is tucked away.

I think updating the pics to v1.6 of the bb and the new bracket and updating some labels will help. We're taking the updated pics tomorrow

@cjsha Do you have the editable documents of these pics that have labels?