[xla:cpu] Disable SVE LLVM codegen by default on AArch64 CPUs.

[copybara-service]

[xla:cpu] Disable SVE LLVM codegen by default on AArch64 CPUs.

There are many missing SVE lowerings in LLVM, especially for bf16 type. This causes program termination on SVE-available machines such as Google Axion. Example error:

LLVM ERROR: Cannot select: 0xf7eb74164950: nxv4bf16 = AArch64ISD::UINT_TO_FP_MERGE_PASSTHRU 0xf7eb74186d60, 0xf7eb74186200, undef:nxv4bf16
  0xf7eb74186d60: nxv4i1 = AArch64ISD::PTRUE TargetConstant:i32<31>
    0xf7eb74191580: i32 = TargetConstant<31>
  0xf7eb74186200: nxv4i32,ch = load<(invariant load (<vscale x 1 x s32>) from %ir.scevgep16, !noalias !5), zext from nxv4i8> 0xf7eb740d8830, 0xf7eb74194070, undef:i64
    0xf7eb74194070: i64 = add 0xf7eb741922f0, 0xf7eb74193c10
      0xf7eb741922f0: i64,ch = CopyFromReg 0xf7eb740d8830, Register:i64 %7
        0xf7eb74191e90: i64 = Register %7
      0xf7eb74193c10: i64,ch = CopyFromReg 0xf7eb740d8830, Register:i64 %11
        0xf7eb74192750: i64 = Register %11
    0xf7eb74186350: i64 = undef
  0xf7eb74164a30: nxv4bf16 = undef
In function: convert.2_kernel
Fatal Python error: Aborted

Since most AArch64 machines still use 128-bit registers, SVE and NEON shouldn't have significant performance difference, so we disable SVE codegen in public builds for the time being.

After JAX uses an XLA commit that has changes from this PR, the following JAX tests will pass on Axion:

bazel test //tests:shape_poly_test_cpu --test_filter=*test_harness_vmap_convert_element_type_dtypes_to_dtypes_shape_bool_100_100_olddtype_bool_newdtype_bfloat16*

bazel test //tests:export_harnesses_multi_platform_test_cpu --test_filter=*test_prim_convert_element_type_dtypes_to_dtypes_shape_uint8_100_100_olddtype_uint8_newdtype_bfloat16* 

Add --test_env=XLA_FLAGS=--xla_cpu_max_isa="" to the options to get the errors back.