Z-Core RV32IMZicsr

Z-Core now implements the RISC-V Zicsr Extension and a subset of the Machine-Mode (M-mode) Privileged Architecture (Privileged Spec v1.12). This enables:

• CSR Register Access: Atomic read-modify-write access to Control and Status Registers via 6 instruction variants.
• Trap Handling Infrastructure: Unified trap entry/exit logic for both Exceptions (synchronous) and Interrupts (asynchronous).
• Performance Counters: Hardware cycle and retired instruction counters (mcycle, minstret).

Z-Core implements M-mode only. Exceptions (Illegal Instruction, ECALL, EBREAK, Misaligned Access) and Interrupts (External, Software, Timer) are fully supported and validated via RISCOF.

Z-Core RV32IM ISA Support

Z-Core now works with RV32IM ISA.

New Features

• RV32IM Support (RISCOF Compliance)
• New Architecture Diagrams
• Revised Documentation

Pipelined RV32I Processor

Z-Core 0.2.0 Alpha

This release is the successor of the Z-Core Multi-Cycle RV32I processor.

It enhances the performance by enabling Pipelining, Hazard Detection, and Operand Forwarding. This new version of the Z-Core processor successfully passes all 41 RISCOF tests for the RV32I Architecture.

New features

• Pipelined RV32I Processor Implementation
• Hazard Detection and Handling
• Operand Forwarding
• AXI4-Lite GPIO Module
• AXI4-Lite UART Module

Full Changelog: https://github.com/paudiaz99/Z-Core/commits/v0.2.0-alpha