preliminary designs
| function | C++ model | Verilog | Testbench |
|---|---|---|---|
| add (vec-vec) | ✅ | ✅ | ✏️ |
| multiply (scalar-vec) | ❌ | ❌ | ❌ |
| multiply (vec-vec) | ❌ | ❌ | ❌ |
| dot product (vector) | ✅ | ✅ | ✅ |
| broadcast (scalar -> vector) | 😐 | ✅ | ✅ |
| conversion vector(fp32 -> mxint8) | ❌ | ❌ | ❌ |
| conversion vector(mxint8 -> fp32) | ❌ | ❌ | ❌ |
| sum (vector -> scalar) | ✅ | ✅ | ✅ |
| negate (vector -> vector) | 😐 | ✅ | ✅ |
For vector add, subtract, multiply, divide, inspiration can be taken from the scalar equivalents in FP32 implemented here in C++.