Skip to content
Open
Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
46 commits
Select commit Hold shift + click to select a range
99b52ed
Update for fpga
owenchj0 Oct 22, 2019
68f735e
Update for pulpissimo to PULP
owenchj0 Oct 22, 2019
41e9c5d
Update for seperating domain
owenchj0 Oct 22, 2019
2cf0e46
Update emu - TODO
owenchj0 Oct 22, 2019
5ce4291
Update pulpemu rtl_list
owenchj0 Oct 22, 2019
25918fe
Update for fpga
owenchj0 Oct 22, 2019
d4b2831
Update fpga
owenchj0 Oct 22, 2019
8a60506
Update pulpemu.sv
owenchj0 Oct 23, 2019
a992a3c
Update for boot rom
owenchj0 Oct 23, 2019
9a0f491
Update for fpga
owenchj0 Oct 23, 2019
335b5d1
fixed padframe
anga93 Oct 23, 2019
de938b1
added pad_functional
anga93 Oct 23, 2019
db6adc6
modified pad frame
anga93 Oct 24, 2019
5b4a72b
Remove pull up down
owenchj0 Oct 24, 2019
6c2e434
fixed pin names
anga93 Oct 24, 2019
5553e16
Add fpga clk gen
owenchj0 Oct 24, 2019
28f39bd
updated pulpemu for new clk srcs
anga93 Oct 25, 2019
05b7bd1
Update pin
owenchj0 Oct 25, 2019
fa633b6
Fix clk wiz module syntax error
owenchj0 Oct 25, 2019
a6a90e5
Delete useless file
owenchj0 Oct 25, 2019
195a376
Update to add BUFGCE
owenchj0 Oct 25, 2019
1cf3471
Update for fpga sim
owenchj0 Oct 29, 2019
fe06cda
Update for netlist simu
owenchj0 Oct 29, 2019
465dc8c
Fix cpu reset and fpga sim issue
owenchj0 Oct 30, 2019
c70aa4d
change clk prop strategy
anga93 Nov 14, 2019
fa5bcc4
add parameter for HPWE
anga93 Nov 19, 2019
527f75d
set HWPE and FPU in Soc to zero
anga93 Nov 19, 2019
486fd7a
add PU and PD
anga93 Nov 19, 2019
b05a543
align top to pulpissimo
anga93 Nov 19, 2019
c35c605
add xilinx clk gating to src
anga93 Nov 19, 2019
61e9ea8
checkout right branch for fpga flow
anga93 Nov 19, 2019
99ab3d7
add xilinx clk and slow clk gen
anga93 Dec 5, 2019
2192e93
add xilinx clk gating IP
anga93 Dec 5, 2019
7903fe3
update for FMC ext board. clean up needed
anga93 Dec 10, 2019
a02d9ad
add fpga scripts
anga93 Jan 22, 2020
ad12589
clean up pulpemu
anga93 Feb 3, 2020
da1eb49
add xilinx ips
anga93 Feb 18, 2020
8c33fdd
fix constraints
anga93 Mar 11, 2020
5810cde
add nex xilinx macro
anga93 Mar 11, 2020
ec83eb8
add README for FPGA configuration
anga93 Mar 12, 2020
03d001a
fix for new reset
anga93 Apr 9, 2020
1e29004
fix reset of pulp fpga
anga93 Apr 9, 2020
a93c472
Update for pulp master fpga
owenchj0 Jul 27, 2020
80de646
fpga scripts: replace specific version of vivado with generic one
anga93 Oct 22, 2020
5ed81fc
fpga scripts: clean-up files and update readme
anga93 Oct 22, 2020
0ec6b94
bump pulp cluster to newest tag
anga93 Oct 22, 2020
File filter

Filter by extension

Filter by extension

Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
10 changes: 10 additions & 0 deletions .gitignore
Original file line number Diff line number Diff line change
@@ -0,0 +1,10 @@
fpga
install
ips
ipstools
pulp-builder
pulp-rt-examples
*mk
*pyc
*.f
*.json
35 changes: 30 additions & 5 deletions fpga/.gitignore
Original file line number Diff line number Diff line change
@@ -1,5 +1,30 @@
pulpissimo/*
pulpissimo_genesys2.bin
pulpissimo_genesys2.bit
pulpissimo_zcu104.bin
pulpissimo_zcu104.bit
pulp_cluster/*.edf
pulp_cluster/*.v
pulpemu/pulpemu.*
ips/*/ip/
*.jou
*.log
*.cache/
*.hw/
*.runs/
*.srcs/
*.xpr
*.xci
*.Xil
*.mif
*.swp
vivado_*
reports*
*bin
*bit

sim/.cxl*
sim/ips_inputs
sim/vcompile/rtl/*
sim/vcompile/ips/*
sim/models
sim/modelsim.ini.bak
*sim.v
*sdf
*.mcs
*.prm
96 changes: 48 additions & 48 deletions fpga/Makefile
Original file line number Diff line number Diff line change
@@ -1,48 +1,48 @@
.DEFAULT_GOAL:=help

all: genesys2 zcu104 nexys_video ## Generates the bitstream for all supported boards board.

clean_all: clean_genesys2 clean_zcu104 clean_nexys_video ## Removes synthesis output and bitstreams for all boards.

genesys2: ## Generates the bistream for the genesys2 board
cd pulpissimo-genesys2; make all
cp pulpissimo-genesys2/pulpissimo_genesys2.runs/impl_1/xilinx_pulpissimo.bit pulpissimo_genesys2.bit
cp pulpissimo-genesys2/pulpissimo_genesys2.runs/impl_1/xilinx_pulpissimo.bin pulpissimo_genesys2.bin
@echo "Bitstream generation for genesys2 board finished. The bitstream Configuration Memory File was copied to ./pulpissimo_genesys2.bit and ./pulpissimo_genesys2.bin"

clean_genesys2: ## Removes all bitstreams, *.log files and vivado related files (rm -rf vivado*) for the genesys2 board.
cd pulpissimo-genesys2; make clean
rm -f pulpissimo_genesys2.bit
rm -f pulpissimo_genesys2.bin

zcu104: ## Generates the bistream for the zcu104 board
cd pulpissimo-zcu104; make all
cp pulpissimo-zcu104/pulpissimo_zcu104.runs/impl_1/xilinx_pulpissimo.bit pulpissimo_zcu104.bit
cp pulpissimo-zcu104/pulpissimo_zcu104.runs/impl_1/xilinx_pulpissimo.bin pulpissimo_zcu104.bin
@echo "Bitstream generation for zcu104 board finished. The bitstream Configuration Memory File was copied to ./pulpissimo_zcu104.bit and ./pulpissimo_zcu104.bin"

clean_zcu104: ## Removes all bitstreams, *.log files and vivado related files (rm -rf vivado*) for the zcu104 board.
cd pulpissimo-zcu104; make clean
rm -f pulpissimo_zcu104.bit
rm -f pulpissimo_zcu104.bin

nexys_video: ## Generates the bistream for the nexys_video board
cd pulpissimo-nexys_video; make all
cp pulpissimo-nexys_video/pulpissimo-nexys_video.runs/impl_1/xilinx_pulpissimo.bit pulpissimo_nexys_video.bit
cp pulpissimo-nexys_video/pulpissimo-nexys_video.runs/impl_1/xilinx_pulpissimo.bin pulpissimo_nexys_video.bin
@echo "Bitstream generation for nexys_video board finished. The bitstream Configuration Memory File was copied to ./pulpissimo_nexys_video.bit and ./pulpissimo_nexys_video.bin"

clean_nexys_video: ## Removes all bitstreams, *.log files and vivado related files (rm -rf vivado*) for the nexys_video board.
cd pulpissimo-nexys_video; make clean
rm -f pulpissimo_nexys_video.bit
rm -f pulpissimo_nexys_video.bin

help: ## Show this help message
@echo "PULPissimo on FPGA"
@echo ""
@echo "Call make with one of the supported FPGA boards as arguments to generate the bitstream in the corresponding folder. "
@echo "E.g. 'make genesys2' to generate the bitstream for the genesys2 board in pulpissimo-genesy2 subdirectory."
@echo "By default make invokes 'vivado' to start Xilinx Vivado. This behaviour can be overriden by setting the make variable 'VIVADO'"
@echo "e.g. make genesys2 VIVADO='vivado-2018.3 vivado' for ETH centos machines."
@echo ""
@grep -E '^[a-zA-Z0-9_-]+:.*?## .*$$' $(MAKEFILE_LIST) | sort | awk 'BEGIN {FS = ":.*?## "}; {printf "\033[36m%-30s\033[0m %s\n", $$1, $$2}'
include fpga-settings.mk

all: synth impl

gui:
cd pulpemu; make clean-impl gui

impl:
cd pulpemu; make clean-impl impl

ips: mem clk

generate_bitstream: ips synth-pulpcluster synth-pulpemu

mem:
cd ips/xilinx_interleaved_ram; make clean all
cd ips/xilinx_private_ram; make clean all
cd ips/xilinx_rom_bank_2048x32; make clean all
cd ips/xilinx_tcdm_bank_1024x32; make clean all
cd ips/xilinx_tcdm_bank_2048x32; make clean all

clk: ## Synthesizes the Xilinx Clocking Manager IPs
cd ips/xilinx_clk_mngr; make clean all
cd ips/xilinx_slow_clk_mngr; make clean all

synth: synth-pulpcluster synth-pulpemu

synth-pulpcluster:
cd pulp_cluster; make clean all

synth-pulpemu:
cd pulpemu; make clean all

cleanall: clean-ips clean-ulpcluster clean-pulpemu

clean-ulpcluster:
cd pulp_cluster; make clean

clean-pulpemu:
cd pulpemu; make clean

clean-ips:
cd ips/xilinx_interleaved_ram; make clean
cd ips/xilinx_private_ram; make clean
cd ips/xilinx_rom_bank_2048x32; make clean
cd ips/xilinx_tcdm_bank_1024x32; make clean
cd ips/xilinx_tcdm_bank_2048x32; make clean
cd ips/xilinx_clk_mngr; make clean
Loading