FROMLIST: arm64: dts: qcom: sa8775p: add GPDSP fastrpc-compute-cb nodes #116
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sa8775p-ride firmware supports vendor-defined SYSTEM_RESET2 types. Describe the reset types: "bootloader" will cause device to reboot and stop in the bootloader's fastboot mode. "edl" will cause device to reboot into "emergency download mode", which permits loading images via the Firehose protocol. Link: https://lore.kernel.org/r/20250303-arm-psci-system_reset2-vendor-reboots-v9-5-b2cf4a20feda@oss.qualcomm.com Co-developed-by: Shivendra Pratap <[email protected]> Signed-off-by: Shivendra Pratap <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Signed-off-by: Elliot Berman <[email protected]>
…board QCS9075 is compatible Industrial-IOT grade variant of SA8775p SOC. Unlike QCS9100, it doesn't have safety monitoring feature of Safety-Island(SAIL) subsystem, which affects thermal management. qcs9075-iq-9075-evk board is based on QCS9075 SOC. Link: https://lore.kernel.org/r/[email protected] Acked-by: Rob Herring (Arm) <[email protected]> Acked-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Wasim Nazir <[email protected]>
QCS9075 is an IoT variant of SA8775P SOC, most notably without safety monitoring feature of Safety Island(SAIL) subsystem. Add a new device tree file for the QCS9075 IoT SOC, which inherits changes from the SA8775P SOC. Update the memory map to reflect the differences between the two SOCs. As part of the memory-map updates, introduce new carveouts for gunyah_md and pil dtb, and adjust the size and base address of the PIL carveout to accomodate the changes. Increase the size of the video/camera PIL carveout without breaking any features. Reduce the size of the trusted apps carveout to meet IoT requirements. Remove audio_mdf_mem, tz_ffi_mem, and their corresponding scm references, as they are not required for IoT parts. Link: https://lore.kernel.org/r/[email protected] Co-developed-by: Pratyush Brahma <[email protected]> Signed-off-by: Pratyush Brahma <[email protected]> Co-developed-by: Prakash Gupta <[email protected]> Signed-off-by: Prakash Gupta <[email protected]> Signed-off-by: Wasim Nazir <[email protected]>
Add initial device tree support for IQ-9075-EVK board, based on Qualcomm's QCS9075 SOC. Implement basic features like uart/ufs to enable boot to shell. Link: https://lore.kernel.org/r/[email protected] Co-developed-by: Rakesh Kota <[email protected]> Signed-off-by: Rakesh Kota <[email protected]> Co-developed-by: Sayali Lokhande <[email protected]> Signed-off-by: Sayali Lokhande <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Signed-off-by: Wasim Nazir <[email protected]>
Add RTC node, the RTC is controlled by PMIC device via spmi bus. Link: https://lore.kernel.org/r/[email protected] Reviewed-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Tingguo Cheng <[email protected]>
Add Epoch Subsystem (EPSS) L3 interconnect provider node on SA8775P SoCs. L3 instances on this SoC are same as SM8250 and SC7280 SoCs. These SoCs use EPSS_L3_PERF register instead of REG_L3_VOTE register for programming the perf level. This is taken care in the data associated with the target specific compatible. Since, the HW is same in the all SoCs with EPSS support, using the same generic compatible for all. Link: https://lore.kernel.org/r/[email protected] Reviewed-by: Konrad Dybcio <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Raviteja Laggyshetty <[email protected]>
Add OPP tables required to scale DDR and L3 per freq-domain on SA8775P platform. If a single OPP table is used for both CPU domains, then _allocate_opp_table() won't be invoked for CPU4 but instead CPU4 will be added as device under the CPU0 OPP table. Due to this, dev_pm_opp_of_find_icc_paths() won't be invoked for CPU4 device and hence CPU4 won't be able to independently scale it's interconnects. Both CPU0 and CPU4 devices will scale the same ICC path which can lead to one device overwriting the BW vote placed by other device. Hence CPU0 and CPU4 require separate OPP tables to allow independent scaling of DDR and L3 frequencies for each CPU domain, with the final DDR and L3 frequencies being an aggregate of both. Link: https://lore.kernel.org/r/[email protected] Co-developed-by: Shivnandan Kumar <[email protected]> Signed-off-by: Shivnandan Kumar <[email protected]> Signed-off-by: Raviteja Laggyshetty <[email protected]> Signed-off-by: Jagadeesh Kona <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]>
Video node enables video on Qualcomm SA8775P platform. Link: https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux.git/commit/?h=for-next&id=7bc95052c64f45c24affbb7636489dc9a1c2a982 Reviewed-by: Bryan O'Donoghue <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Signed-off-by: Vikash Garodia <[email protected]> Signed-off-by: Dikshita Agarwal <[email protected]>
Enable video nodes on the sa8775p-ride board and point to the appropriate firmware files. Link: https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux.git/commit/?h=for-next&id=d33ad6600453fbcf6a9275864ad120079bd540da Reviewed-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Vikash Garodia <[email protected]> Signed-off-by: Dikshita Agarwal <[email protected]>
Add GDSP0 and GDSP1 fastrpc compute-cb nodes for sa8775p SoC. Link: https://lore.kernel.org/linux-arm-msm/[email protected]/ Signed-off-by: Ling Xu <[email protected]>
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Add GDSP0 and GDSP1 fastrpc compute-cb nodes for sa8775p SoC.