GitHub - rcjng/bcd-adder: A 4-bit BCD adder using a 4-bit ripple carry adder implemented in VHDL onto an Altera MAX10 DE10-Lite FPGA

rcjng / bcd-adder Public

A 4-bit BCD adder using a 4-bit ripple carry adder implemented in VHDL onto an Altera MAX10 DE10-Lite FPGA

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Name		Name	Last commit message	Last commit date
Latest commit History 3 Commits
DE10_LITE_Golden_Top.v		DE10_LITE_Golden_Top.v
bcd2_to_seg7.vhd		bcd2_to_seg7.vhd
bcd_adder.vhd		bcd_adder.vhd
bcd_adder_top_level.vhd		bcd_adder_top_level.vhd
bin4_to_seg7.vhd		bin4_to_seg7.vhd
bin5_to_bcd2.vhd		bin5_to_bcd2.vhd
full_adder.vhd		full_adder.vhd
rc_adder.vhd		rc_adder.vhd

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