GitHub - rcjng/bcd-adder-alt: An alternate implementation of a 4-bit BCD adder using a 4-bit ripple carry adder implemented in VHDL onto an Altera MAX10 DE10-Lite FPGA

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An alternate implementation of a 4-bit BCD adder using a 4-bit ripple carry adder implemented in VHDL onto an Altera MAX10 DE10-Lite FPGA

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Name		Name	Last commit message	Last commit date
Latest commit History 1 Commit
DE10_LITE_Golden_Top.v		DE10_LITE_Golden_Top.v
bcd2_to_seg7.vhd		bcd2_to_seg7.vhd
bcd_adder_alt.vhd		bcd_adder_alt.vhd
bcd_adder_top_level_alt.vhd		bcd_adder_top_level_alt.vhd

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An alternate implementation of a 4-bit BCD adder using a 4-bit ripple carry adder implemented in VHDL onto an Altera MAX10 DE10-Lite FPGA

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