feat(idl): validated support for virtual memory and S-Mode

[henrikg-qc]

• Added support for Sv32 in mc100-32-riscv-tests configuration.
• Several bug fixes including comparators and bit extraction.
• Added instruction tracing to hit basic block handling.
• Added regression tests for M, C, S extensions.

[henrikg-qc]

Note that wfi test is excluded from the riscv-tests for the regression as SIE CSR is not yet supported.
Awaiting #1046

[codecov]

Codecov Report

✅ All modified and coverable lines are covered by tests.
✅ Project coverage is 46.05%. Comparing base (c1bb236) to head (6ce3562).
⚠️ Report is 1 commits behind head on main.

Additional details and impacted files

@@           Coverage Diff           @@
##             main    #1134   +/-   ##
=======================================
  Coverage   46.05%   46.05%           
=======================================
  Files          11       11           
  Lines        4942     4942           
  Branches     1345     1345           
=======================================
  Hits         2276     2276           
  Misses       2666     2666           

Flag	Coverage Δ
idlc	46.05% <ø> (ø)

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[henrikg-qc]

A extension is not currently part of the MC100-riscv-tests configuration. As the SoC model isn't implementing multiple harts AMO tests will be deferred until the A is added and validated in the ISS model.

[henrikg-qc]

@dhower-qc @ThinkOpenly
Ready when you are 👍

[dhower-qc]

👍

[henrikg-qc]

Follow up issue #1141 created based on @jordancarlin 's comment