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Add test generators for the Smcfiss, Smucfiss, Smpmpind and Sspmpss shadow-stack bundle - #2156

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Add test generators for the Smcfiss, Smucfiss, Smpmpind and Sspmpss shadow-stack bundle#2156
michalchm wants to merge 4 commits into
riscv:act4from
michalchm:shadow-stack

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Adds test generators for four pre-ratification shadow-stack extensions: Smpmpind for indirect PMP CSR access,
Smcfiss and Smucfiss for M-mode and U-mode shadow stacks on PMP, and Sspmpss for S-mode and U-mode shadow stacks
on SPMP. The corresponding extension definitions are proposed in riscv/riscv-unified-db#2510.

Verified against the proposed Sail implementations in riscv/sail-riscv#1864, riscv/sail-riscv#1865,
riscv/sail-riscv#1866 and riscv/sail-riscv#1870. Smpmpind, Smcfiss and Smucfiss were also run against a Spike
fork. Sspmpss has no independent DUT because Spike does not implement SPMP.

Makes the PMP address and configuration registers accessible through the
Smcsrind indirect CSR mechanism and defines pmpcfg.E at MXLEN-1, outside the
direct eight-bit configuration view.

The tests exercise the indirect access path, including that E survives a direct
pmpcfg round-trip.
Enables Zicfiss shadow stacks in M-mode using a PMP entry with pmpcfg.E=1 and
XWR=010, gated by mseccfg.MSSE.

The tests cover the access policy, the reserved encoding with MSSE clear, and
the Smepmp interlock.
Enables Zicfiss shadow stacks in U-mode on M+U harts without S-mode using a PMP
entry with pmpcfg.E=1 and XWR=110, gated by menvcfg.SSE.

The region is configured from M-mode and exercised in U-mode.
Enables Zicfiss shadow stacks for S-mode and U-mode software using an SPMP
region with spmpcfg.XWR=010 and SHARED=0.

The tests cover the configuration path and the access policy at privilege S.
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